Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 692050 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 5797450 1 T1 40745 T2 33 T3 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1700289 1 T1 11323 T2 186 T3 15
values[0x0] 2214264 1 T1 15631 T2 12 T3 5
values[0x1] 2574947 1 T1 17785 T2 20 T3 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 335731 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 6153769 1 T1 42862 T2 96 T3 12



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25269 1 T1 177 T2 3 T37 1
valid_sources[0x01] 26312 1 T1 186 T2 2 T21 461
valid_sources[0x02] 25119 1 T1 150 T5 3 T37 2
valid_sources[0x03] 25174 1 T1 152 T2 3 T21 781
valid_sources[0x04] 26705 1 T1 196 T37 1 T21 476
valid_sources[0x05] 23459 1 T1 158 T37 2 T21 522
valid_sources[0x06] 24104 1 T1 189 T2 1 T21 369
valid_sources[0x07] 25533 1 T1 172 T21 538 T22 341
valid_sources[0x08] 25448 1 T1 143 T21 451 T9 1
valid_sources[0x09] 26167 1 T1 198 T2 3 T21 844
valid_sources[0x0a] 24125 1 T1 176 T2 1 T21 430
valid_sources[0x0b] 24629 1 T1 175 T21 322 T22 360
valid_sources[0x0c] 26360 1 T1 199 T2 2 T37 4
valid_sources[0x0d] 26224 1 T1 195 T2 2 T21 569
valid_sources[0x0e] 25272 1 T1 180 T2 2 T37 4
valid_sources[0x0f] 25050 1 T1 191 T21 397 T22 368
valid_sources[0x10] 24645 1 T1 174 T37 1 T21 690
valid_sources[0x11] 24019 1 T1 180 T2 1 T21 496
valid_sources[0x12] 25867 1 T1 172 T2 1 T37 1
valid_sources[0x13] 26594 1 T1 189 T3 1 T20 67
valid_sources[0x14] 26344 1 T1 148 T2 1 T37 4
valid_sources[0x15] 25630 1 T1 199 T2 3 T21 593
valid_sources[0x16] 25134 1 T1 166 T2 1 T21 608
valid_sources[0x17] 25840 1 T1 188 T2 2 T37 5
valid_sources[0x18] 28951 1 T1 193 T2 1 T21 743
valid_sources[0x19] 26097 1 T1 132 T2 1 T21 562
valid_sources[0x1a] 25842 1 T1 192 T21 273 T22 371
valid_sources[0x1b] 25218 1 T1 183 T21 614 T22 344
valid_sources[0x1c] 23464 1 T1 175 T2 2 T5 3
valid_sources[0x1d] 25312 1 T1 167 T5 3 T37 1
valid_sources[0x1e] 25782 1 T1 163 T2 1 T21 749
valid_sources[0x1f] 26206 1 T1 182 T2 1 T37 4
valid_sources[0x20] 24810 1 T1 156 T5 5 T37 5
valid_sources[0x21] 26740 1 T1 175 T36 193 T37 3
valid_sources[0x22] 25825 1 T1 165 T2 1 T5 1
valid_sources[0x23] 23808 1 T1 187 T28 774 T21 594
valid_sources[0x24] 25291 1 T1 196 T2 1 T21 532
valid_sources[0x25] 23739 1 T1 194 T37 4 T21 301
valid_sources[0x26] 27144 1 T1 144 T2 3 T21 725
valid_sources[0x27] 22854 1 T1 170 T2 1 T5 2
valid_sources[0x28] 24568 1 T1 203 T2 1 T37 2
valid_sources[0x29] 24678 1 T1 172 T21 694 T22 372
valid_sources[0x2a] 25088 1 T1 185 T21 483 T22 358
valid_sources[0x2b] 24613 1 T1 170 T37 1 T21 925
valid_sources[0x2c] 25038 1 T1 194 T2 1 T3 2
valid_sources[0x2d] 23522 1 T1 174 T4 1 T21 497
valid_sources[0x2e] 26970 1 T1 182 T21 589 T22 355
valid_sources[0x2f] 26033 1 T1 175 T37 3 T21 411
valid_sources[0x30] 25565 1 T1 174 T2 2 T5 1
valid_sources[0x31] 25270 1 T1 174 T21 636 T10 1
valid_sources[0x32] 24172 1 T1 201 T5 2 T21 673
valid_sources[0x33] 25569 1 T1 156 T2 1 T21 517
valid_sources[0x34] 26101 1 T1 214 T2 1 T21 527
valid_sources[0x35] 25255 1 T1 178 T4 5 T37 1
valid_sources[0x36] 26523 1 T1 135 T2 1 T4 2
valid_sources[0x37] 25978 1 T1 159 T21 584 T10 1
valid_sources[0x38] 24156 1 T1 185 T2 2 T5 1
valid_sources[0x39] 23466 1 T1 172 T2 3 T3 1
valid_sources[0x3a] 24111 1 T1 197 T2 2 T21 669
valid_sources[0x3b] 24626 1 T1 149 T37 4 T21 595
valid_sources[0x3c] 25139 1 T1 168 T37 2 T21 647
valid_sources[0x3d] 25469 1 T1 180 T37 3 T21 454
valid_sources[0x3e] 24590 1 T1 165 T2 1 T37 1
valid_sources[0x3f] 24656 1 T1 165 T5 1 T37 9
valid_sources[0x40] 24728 1 T1 164 T5 2 T21 718
valid_sources[0x41] 24528 1 T1 169 T3 6 T21 588
valid_sources[0x42] 25184 1 T1 178 T2 1 T21 709
valid_sources[0x43] 25064 1 T1 165 T2 3 T37 1
valid_sources[0x44] 23662 1 T1 161 T2 2 T5 1
valid_sources[0x45] 26239 1 T1 188 T2 1 T5 1
valid_sources[0x46] 25163 1 T1 191 T5 1 T21 316
valid_sources[0x47] 26105 1 T1 157 T37 2 T21 590
valid_sources[0x48] 26519 1 T1 161 T21 566 T22 344
valid_sources[0x49] 25331 1 T1 195 T2 1 T4 1
valid_sources[0x4a] 26370 1 T1 186 T21 690 T22 363
valid_sources[0x4b] 26542 1 T1 170 T2 4 T21 617
valid_sources[0x4c] 27221 1 T1 155 T2 1 T21 387
valid_sources[0x4d] 25697 1 T1 171 T37 2 T21 652
valid_sources[0x4e] 25588 1 T1 198 T2 1 T21 360
valid_sources[0x4f] 23878 1 T1 158 T2 1 T21 500
valid_sources[0x50] 26733 1 T1 165 T21 350 T22 317
valid_sources[0x51] 25406 1 T1 169 T21 496 T22 375
valid_sources[0x52] 26333 1 T1 165 T2 1 T5 2
valid_sources[0x53] 26283 1 T1 212 T2 1 T5 2
valid_sources[0x54] 25411 1 T1 192 T2 2 T37 2
valid_sources[0x55] 25881 1 T1 175 T37 2 T21 938
valid_sources[0x56] 26313 1 T1 167 T2 1 T21 557
valid_sources[0x57] 26841 1 T1 182 T5 2 T37 1
valid_sources[0x58] 23499 1 T1 165 T37 1 T21 435
valid_sources[0x59] 26614 1 T1 184 T2 2 T21 521
valid_sources[0x5a] 24431 1 T1 178 T2 1 T21 269
valid_sources[0x5b] 24204 1 T1 194 T2 3 T37 2
valid_sources[0x5c] 24961 1 T1 189 T37 2 T21 465
valid_sources[0x5d] 26518 1 T1 168 T2 4 T21 867
valid_sources[0x5e] 25429 1 T1 155 T2 2 T37 1
valid_sources[0x5f] 25155 1 T1 169 T2 1 T37 2
valid_sources[0x60] 24693 1 T1 157 T2 1 T21 410
valid_sources[0x61] 25989 1 T1 210 T2 3 T21 527
valid_sources[0x62] 24353 1 T1 177 T2 2 T8 61
valid_sources[0x63] 24682 1 T1 194 T37 1 T21 410
valid_sources[0x64] 25833 1 T1 168 T2 1 T21 561
valid_sources[0x65] 24838 1 T1 161 T2 2 T21 520
valid_sources[0x66] 24585 1 T1 162 T37 5 T21 588
valid_sources[0x67] 26137 1 T1 185 T21 343 T10 1
valid_sources[0x68] 26216 1 T1 176 T3 2 T37 1
valid_sources[0x69] 25872 1 T1 176 T2 2 T21 759
valid_sources[0x6a] 28328 1 T1 193 T21 810 T22 335
valid_sources[0x6b] 25823 1 T1 143 T2 2 T5 1
valid_sources[0x6c] 25976 1 T1 169 T2 1 T21 359
valid_sources[0x6d] 23733 1 T1 144 T2 1 T37 5
valid_sources[0x6e] 24918 1 T1 171 T2 1 T21 532
valid_sources[0x6f] 24319 1 T1 169 T2 1 T21 1092
valid_sources[0x70] 23818 1 T1 162 T21 735 T9 3
valid_sources[0x71] 26060 1 T1 169 T2 2 T5 2
valid_sources[0x72] 25661 1 T1 206 T21 265 T22 324
valid_sources[0x73] 25685 1 T1 163 T2 1 T5 5
valid_sources[0x74] 24238 1 T1 166 T5 1 T21 507
valid_sources[0x75] 26124 1 T1 180 T2 1 T5 1
valid_sources[0x76] 27204 1 T1 144 T2 3 T4 7
valid_sources[0x77] 25755 1 T1 170 T21 475 T22 298
valid_sources[0x78] 23989 1 T1 175 T2 1 T5 3
valid_sources[0x79] 26685 1 T1 176 T21 840 T9 1
valid_sources[0x7a] 23849 1 T1 204 T2 1 T4 1
valid_sources[0x7b] 28452 1 T1 151 T2 1 T21 478
valid_sources[0x7c] 24386 1 T1 221 T4 7 T37 1
valid_sources[0x7d] 24355 1 T1 165 T2 1 T3 3
valid_sources[0x7e] 25163 1 T1 185 T4 9 T5 1
valid_sources[0x7f] 27190 1 T1 148 T2 1 T37 7
valid_sources[0x80] 24833 1 T1 174 T2 1 T21 707



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1459605 1 T1 10108 T2 6 T3 3
values[0x0] all_enables biggest_size 2170337 1 T1 15372 T2 11 T3 1
values[0x1] all_enables biggest_size 2167508 1 T1 15265 T2 16 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%