Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2467	1			T1	14		T2	2		T8	6
non_zero_bins[1]	1763	1			T1	9		T2	1		T8	1
zero	8212	1			T1	60		T2	2		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	484	1			T1	2		T28	2		T21	5
uni	3457	1			T1	28		T2	2		T28	13
gen	3755	1			T1	22		T2	1		T3	1
res	789	1			T1	3		T8	5		T28	2
ins	3957	1			T1	28		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8346

1

T1

59

T2

4

T3

2

mubi_true

4096

1

T1

24

T2

1

T8

7

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T14

1

T15

1

T16

1

pass

12392

1

T1

83

T2

5

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	115	1			T28	1		T21	1		T22	2
upd	non_zero_bins[0]	pass	mubi_true	114	1			T28	1		T21	2		T22	1
upd	non_zero_bins[1]	pass	mubi_false	74	1			T22	2		T155	1		T160	1
upd	non_zero_bins[1]	pass	mubi_true	93	1			T1	1		T21	2		T22	1
upd	zero	pass	mubi_false	45	1			T1	1		T133	1		T185	2
upd	zero	pass	mubi_true	43	1			T159	1		T160	1		T248	1
uni	zero	fail	mubi_false	12	1			T114	1		T115	1		T116	1
uni	zero	pass	mubi_false	2477	1			T1	18		T2	2		T28	9
uni	zero	pass	mubi_true	968	1			T1	10		T28	4		T21	21
gen	non_zero_bins[0]	pass	mubi_false	453	1			T1	5		T28	1		T36	1
gen	non_zero_bins[0]	pass	mubi_true	416	1			T1	1		T2	1		T8	3
gen	non_zero_bins[1]	pass	mubi_false	332	1			T1	2		T28	2		T21	3
gen	non_zero_bins[1]	pass	mubi_true	337	1			T1	1		T21	3		T22	4
gen	zero	fail	mubi_false	25	1			T14	1		T15	1		T16	1
gen	zero	pass	mubi_false	1777	1			T1	12		T3	1		T4	1
gen	zero	pass	mubi_true	415	1			T1	1		T28	2		T20	1
res	non_zero_bins[0]	pass	mubi_false	180	1			T8	3		T28	1		T36	1
res	non_zero_bins[0]	pass	mubi_true	200	1			T1	1		T28	1		T21	2
res	non_zero_bins[1]	pass	mubi_false	123	1			T21	1		T9	1		T22	2
res	non_zero_bins[1]	pass	mubi_true	128	1			T1	1		T21	1		T22	1
res	zero	fail	mubi_false	6	1			T164	1		T171	1		T249	1
res	zero	pass	mubi_false	60	1			T155	1		T185	1		T186	1
res	zero	pass	mubi_true	92	1			T1	1		T8	2		T21	1
ins	non_zero_bins[0]	pass	mubi_false	476	1			T1	2		T2	1		T21	4
ins	non_zero_bins[0]	pass	mubi_true	513	1			T1	5		T28	3		T20	1
ins	non_zero_bins[1]	pass	mubi_false	328	1			T1	4		T2	1		T28	1
ins	non_zero_bins[1]	pass	mubi_true	348	1			T8	1		T28	1		T36	1
ins	zero	fail	mubi_false	6	1			T47	1		T99	1		T100	1
ins	zero	fail	mubi_true	1	1			T250	1		-	-		-	-
ins	zero	pass	mubi_false	1857	1			T1	15		T3	1		T4	1
ins	zero	pass	mubi_true	428	1			T1	2		T8	1		T28	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded