Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	229726830	10322428	0	0
boot_gen_cmd_rd_A	229726830	69168	0	0
boot_ins_cmd_rd_A	229726830	78308	0	0
ctrl_rd_A	229726830	70144	0	0
err_code_test_rd_A	229726830	79835	0	0
intr_enable_rd_A	229726830	78181	0	0
max_num_reqs_between_reseeds_rd_A	229726830	69695	0	0
regwen_rd_A	229726830	79973	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	10322428	0	0
T1	185777	67008	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T21	0	225936	0	0
T22	0	133024	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T155	0	156959	0	0
T161	0	99551	0	0
T185	0	117195	0	0
T186	0	359604	0	0
T187	0	104655	0	0
T188	0	183720	0	0
T189	0	75969	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	69168	0	0
T1	185777	2150	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4012	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	12452	0	0
T185	0	3271	0	0
T189	0	2312	0	0
T190	0	1610	0	0
T191	0	4171	0	0
T192	0	1461	0	0
T193	0	3743	0	0
T194	0	3114	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	78308	0	0
T1	185777	2210	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4366	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	14407	0	0
T185	0	3996	0	0
T189	0	2591	0	0
T190	0	1684	0	0
T191	0	4708	0	0
T192	0	1669	0	0
T193	0	4172	0	0
T194	0	3498	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	70144	0	0
T1	185777	2013	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4128	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	13115	0	0
T114	0	4	0	0
T185	0	3508	0	0
T189	0	2197	0	0
T190	0	1491	0	0
T195	0	7	0	0
T196	0	2	0	0
T197	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	79835	0	0
T1	185777	2260	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4459	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	14832	0	0
T185	0	3841	0	0
T189	0	2349	0	0
T190	0	1704	0	0
T191	0	5069	0	0
T192	0	1667	0	0
T193	0	4350	0	0
T194	0	3721	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	78181	0	0
T1	185777	2033	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4176	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	13312	0	0
T54	0	91	0	0
T185	0	4164	0	0
T189	0	2494	0	0
T190	0	1874	0	0
T196	0	58	0	0
T198	0	96	0	0
T199	0	46	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	69695	0	0
T1	185777	1952	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4049	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	12309	0	0
T185	0	3191	0	0
T189	0	2269	0	0
T190	0	1339	0	0
T191	0	4466	0	0
T192	0	1467	0	0
T193	0	3776	0	0
T194	0	3110	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229726830	79973	0	0
T1	185777	2457	0	0
T2	3979	0	0	0
T3	1441	0	0	0
T4	1622	0	0	0
T5	676	0	0	0
T8	2498	0	0	0
T20	2471	0	0	0
T22	0	4366	0	0
T28	23697	0	0	0
T36	1837	0	0	0
T37	2875	0	0	0
T48	0	14300	0	0
T185	0	3940	0	0
T189	0	2670	0	0
T190	0	1513	0	0
T191	0	4655	0	0
T192	0	1726	0	0
T193	0	4153	0	0
T194	0	3612	0	0