Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	139	1			T36	1		T28	1		T30	1
auto_req_mode	122	1			T8	1		T9	1		T10	1
sw_mode	3013	1			T1	1		T21	8		T35	17

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

275

1

T8

1

T36

1

T50

1

single

111

1

T10

1

T86

1

T71

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1363	1			T1	1		T8	1		T36	1
auto[2]	158	1			T26	1		T38	1		T262	3
auto[3]	164	1			T27	1		T154	9		T241	1
auto[4]	96	1			T28	1		T37	1		T263	67
auto[5]	85	1			T44	1		T264	1		T265	55
auto[6]	215	1			T177	1		T266	1		T267	63
auto[7]	1193	1			T21	8		T35	17		T10	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	82	1			T36	1		T30	1		T71	1
auto[1]	auto_req_mode	70	1			T8	1		T9	1		T86	1
auto[1]	sw_mode	1211	1			T1	1		T50	1		T22	41
auto[2]	boot_req_mode	3	1			T268	1		T269	1		T270	1
auto[2]	auto_req_mode	6	1			T26	1		T38	1		T271	1
auto[2]	sw_mode	149	1			T262	3		T272	1		T273	66
auto[3]	boot_req_mode	5	1			T274	1		T275	1		T276	1
auto[3]	auto_req_mode	4	1			T241	1		T277	1		T278	1
auto[3]	sw_mode	155	1			T27	1		T154	9		T279	52
auto[4]	boot_req_mode	9	1			T28	1		T280	1		T62	1
auto[4]	auto_req_mode	5	1			T37	1		T281	1		T282	1
auto[4]	sw_mode	82	1			T263	67		T283	1		T284	1
auto[5]	boot_req_mode	2	1			T285	1		T286	1		-	-
auto[5]	auto_req_mode	2	1			T287	1		T63	1		-	-
auto[5]	sw_mode	81	1			T44	1		T264	1		T265	55
auto[6]	boot_req_mode	4	1			T288	1		T289	1		T290	1
auto[6]	auto_req_mode	3	1			T177	1		T291	1		T292	1
auto[6]	sw_mode	208	1			T266	1		T267	63		T293	1
auto[7]	boot_req_mode	34	1			T39	1		T47	1		T176	1
auto[7]	auto_req_mode	32	1			T10	1		T31	1		T41	1
auto[7]	sw_mode	1127	1			T21	8		T35	17		T23	70