Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5523861

1

T1

9

T2

10

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1643236	1			T1	22		T2	4		T3	5
values[0x0]	2109007	1			T1	2		T2	5		T3	1
values[0x1]	2450728	1			T1	5		T2	8		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	335591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5867380

1

T1

15

T2

11

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24310	1			T35	3		T22	305		T23	474
valid_sources[0x01]	24695	1			T3	2		T35	6		T50	2
valid_sources[0x02]	24191	1			T35	8		T8	5		T22	268
valid_sources[0x03]	24094	1			T35	5		T22	275		T86	21
valid_sources[0x04]	23973	1			T35	9		T22	301		T23	458
valid_sources[0x05]	22707	1			T35	3		T22	242		T10	1
valid_sources[0x06]	24237	1			T35	4		T50	2		T22	260
valid_sources[0x07]	24594	1			T35	8		T22	297		T23	485
valid_sources[0x08]	24917	1			T1	1		T35	5		T22	270
valid_sources[0x09]	24038	1			T35	5		T50	1		T22	294
valid_sources[0x0a]	24102	1			T35	9		T22	271		T10	1
valid_sources[0x0b]	24224	1			T35	9		T22	320		T10	2
valid_sources[0x0c]	24009	1			T35	5		T22	301		T10	2
valid_sources[0x0d]	23443	1			T35	5		T36	1		T22	276
valid_sources[0x0e]	25538	1			T35	1		T8	4		T22	247
valid_sources[0x0f]	22962	1			T35	7		T22	302		T23	469
valid_sources[0x10]	24291	1			T35	2		T22	305		T23	481
valid_sources[0x11]	24289	1			T35	11		T36	1		T22	292
valid_sources[0x12]	23738	1			T35	3		T22	274		T23	447
valid_sources[0x13]	24731	1			T35	13		T36	2		T22	266
valid_sources[0x14]	24160	1			T35	8		T22	253		T23	447
valid_sources[0x15]	24807	1			T35	1		T22	284		T23	463
valid_sources[0x16]	23210	1			T35	4		T50	1		T22	271
valid_sources[0x17]	24022	1			T1	2		T35	5		T22	287
valid_sources[0x18]	23583	1			T22	277		T23	468		T24	216
valid_sources[0x19]	24485	1			T1	1		T35	14		T22	294
valid_sources[0x1a]	23518	1			T35	4		T22	288		T23	464
valid_sources[0x1b]	24489	1			T35	6		T22	338		T23	487
valid_sources[0x1c]	24470	1			T35	6		T22	284		T10	1
valid_sources[0x1d]	23439	1			T35	9		T22	315		T23	480
valid_sources[0x1e]	22703	1			T2	1		T35	7		T22	297
valid_sources[0x1f]	22320	1			T35	11		T36	1		T50	1
valid_sources[0x20]	23515	1			T35	12		T8	2		T22	311
valid_sources[0x21]	23947	1			T35	9		T36	1		T22	275
valid_sources[0x22]	24627	1			T2	2		T35	9		T36	3
valid_sources[0x23]	23308	1			T1	1		T35	11		T36	1
valid_sources[0x24]	25034	1			T35	3		T22	311		T10	1
valid_sources[0x25]	25404	1			T35	4		T22	272		T10	2
valid_sources[0x26]	24439	1			T35	7		T22	263		T23	441
valid_sources[0x27]	23305	1			T35	3		T8	28		T22	283
valid_sources[0x28]	23064	1			T35	4		T22	315		T10	1
valid_sources[0x29]	25389	1			T35	1		T36	3		T50	1
valid_sources[0x2a]	22974	1			T35	8		T22	300		T10	1
valid_sources[0x2b]	25471	1			T35	14		T36	1		T22	299
valid_sources[0x2c]	24438	1			T35	4		T22	269		T10	1
valid_sources[0x2d]	23039	1			T35	19		T22	288		T10	1
valid_sources[0x2e]	24401	1			T35	8		T22	279		T23	495
valid_sources[0x2f]	23267	1			T35	8		T22	337		T23	450
valid_sources[0x30]	23531	1			T35	8		T50	1		T22	232
valid_sources[0x31]	22719	1			T35	8		T22	273		T23	497
valid_sources[0x32]	24812	1			T35	3		T36	3		T22	279
valid_sources[0x33]	24647	1			T35	4		T36	1		T50	1
valid_sources[0x34]	24406	1			T35	5		T22	274		T23	444
valid_sources[0x35]	23801	1			T1	1		T35	4		T36	1
valid_sources[0x36]	24865	1			T35	6		T22	290		T10	1
valid_sources[0x37]	25590	1			T35	5		T22	268		T23	487
valid_sources[0x38]	23588	1			T35	2		T22	302		T10	1
valid_sources[0x39]	23732	1			T35	11		T22	307		T23	502
valid_sources[0x3a]	23068	1			T1	1		T35	9		T22	296
valid_sources[0x3b]	23051	1			T35	11		T50	2		T22	272
valid_sources[0x3c]	24274	1			T35	3		T50	1		T22	305
valid_sources[0x3d]	25010	1			T35	14		T22	306		T10	1
valid_sources[0x3e]	23802	1			T35	7		T22	273		T10	5
valid_sources[0x3f]	22754	1			T1	1		T2	2		T35	12
valid_sources[0x40]	24541	1			T35	8		T22	316		T10	1
valid_sources[0x41]	23732	1			T35	6		T22	306		T23	526
valid_sources[0x42]	24067	1			T35	7		T22	324		T10	2
valid_sources[0x43]	25318	1			T35	1		T22	270		T23	479
valid_sources[0x44]	23112	1			T35	2		T22	267		T10	1
valid_sources[0x45]	25042	1			T35	8		T36	1		T22	297
valid_sources[0x46]	24755	1			T35	4		T22	288		T23	450
valid_sources[0x47]	24213	1			T2	1		T35	2		T36	1
valid_sources[0x48]	24448	1			T35	4		T22	285		T23	417
valid_sources[0x49]	24147	1			T35	6		T8	11		T22	304
valid_sources[0x4a]	24817	1			T1	1		T35	9		T50	1
valid_sources[0x4b]	24395	1			T35	6		T22	318		T23	462
valid_sources[0x4c]	24363	1			T35	9		T22	266		T10	1
valid_sources[0x4d]	25452	1			T35	7		T50	1		T22	277
valid_sources[0x4e]	24907	1			T3	1		T35	4		T22	300
valid_sources[0x4f]	23265	1			T35	11		T22	313		T23	413
valid_sources[0x50]	24648	1			T35	10		T22	278		T10	1
valid_sources[0x51]	23814	1			T2	1		T35	12		T50	1
valid_sources[0x52]	24500	1			T35	11		T22	262		T10	1
valid_sources[0x53]	23491	1			T35	15		T22	313		T23	467
valid_sources[0x54]	23860	1			T3	1		T35	5		T22	290
valid_sources[0x55]	23936	1			T35	7		T22	327		T23	454
valid_sources[0x56]	23275	1			T1	1		T35	4		T22	274
valid_sources[0x57]	25756	1			T35	6		T50	1		T22	257
valid_sources[0x58]	24414	1			T35	9		T36	4		T22	275
valid_sources[0x59]	25262	1			T35	2		T22	299		T10	1
valid_sources[0x5a]	23198	1			T2	1		T35	1		T36	1
valid_sources[0x5b]	23438	1			T35	3		T22	282		T10	2
valid_sources[0x5c]	24535	1			T35	7		T36	2		T22	308
valid_sources[0x5d]	25356	1			T1	1		T35	6		T50	1
valid_sources[0x5e]	23934	1			T35	1		T22	235		T10	1
valid_sources[0x5f]	26622	1			T35	5		T22	268		T23	499
valid_sources[0x60]	25391	1			T35	1		T22	268		T23	475
valid_sources[0x61]	25391	1			T35	8		T22	285		T23	486
valid_sources[0x62]	24555	1			T35	8		T22	268		T23	497
valid_sources[0x63]	24622	1			T35	3		T22	283		T23	443
valid_sources[0x64]	25625	1			T35	8		T22	262		T23	510
valid_sources[0x65]	24737	1			T35	3		T22	283		T23	458
valid_sources[0x66]	24970	1			T35	14		T22	295		T10	1
valid_sources[0x67]	22670	1			T35	4		T50	1		T22	290
valid_sources[0x68]	24402	1			T35	10		T22	288		T23	493
valid_sources[0x69]	24375	1			T35	9		T22	280		T23	483
valid_sources[0x6a]	24280	1			T35	4		T22	273		T23	481
valid_sources[0x6b]	24657	1			T35	4		T50	2		T22	280
valid_sources[0x6c]	24307	1			T35	8		T22	284		T10	3
valid_sources[0x6d]	25819	1			T1	1		T2	1		T35	11
valid_sources[0x6e]	23834	1			T35	12		T36	1		T22	293
valid_sources[0x6f]	24226	1			T35	12		T50	1		T22	289
valid_sources[0x70]	24191	1			T35	3		T22	282		T23	510
valid_sources[0x71]	24642	1			T35	6		T36	1		T22	257
valid_sources[0x72]	23092	1			T35	5		T50	2		T22	285
valid_sources[0x73]	24990	1			T35	5		T8	3		T22	291
valid_sources[0x74]	23628	1			T35	2		T50	1		T22	272
valid_sources[0x75]	23261	1			T2	2		T35	10		T36	1
valid_sources[0x76]	25627	1			T35	4		T36	1		T22	274
valid_sources[0x77]	24434	1			T35	7		T50	1		T22	303
valid_sources[0x78]	24081	1			T35	5		T22	282		T23	486
valid_sources[0x79]	24372	1			T35	5		T22	306		T23	459
valid_sources[0x7a]	24499	1			T35	6		T50	4		T22	252
valid_sources[0x7b]	24639	1			T3	3		T35	15		T50	1
valid_sources[0x7c]	23079	1			T1	2		T35	10		T22	288
valid_sources[0x7d]	24592	1			T35	5		T36	1		T50	1
valid_sources[0x7e]	24199	1			T35	7		T22	278		T23	515
valid_sources[0x7f]	24043	1			T35	5		T22	284		T23	467
valid_sources[0x80]	23980	1			T35	3		T22	306		T23	436

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1394617

1

T1

4

T2

2

T3

1

values[0x0]

all_enables

biggest_size

2066281

1

T1

2

T2

3

T4

6

values[0x1]

all_enables

biggest_size

2062963

1

T1

3

T2

5

T3

3