Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2537	1			T21	8		T35	16		T8	3
non_zero_bins[1]	1839	1			T21	4		T35	13		T8	4
zero	8687	1			T1	3		T2	4		T4	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	524	1			T21	2		T35	2		T22	5
uni	3711	1			T1	1		T21	9		T35	22
gen	3850	1			T1	1		T2	2		T4	1
res	768	1			T21	2		T35	3		T8	4
ins	4210	1			T1	1		T2	2		T4	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8903

1

T1

2

T4

2

T14

1

mubi_true

4160

1

T1

1

T2

4

T14

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T15

1

T16

1

T17

1

pass

13013

1

T1

3

T2

4

T4

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	119	1			T21	1		T35	1		T22	1
upd	non_zero_bins[0]	pass	mubi_true	131	1			T22	3		T23	8		T24	3
upd	non_zero_bins[1]	pass	mubi_false	87	1			T22	1		T23	1		T24	8
upd	non_zero_bins[1]	pass	mubi_true	88	1			T35	1		T23	5		T24	1
upd	zero	pass	mubi_false	54	1			T21	1		T23	3		T24	1
upd	zero	pass	mubi_true	45	1			T23	1		T143	1		T144	1
uni	zero	fail	mubi_false	12	1			T15	1		T16	1		T128	1
uni	zero	pass	mubi_false	2682	1			T21	7		T35	17		T36	2
uni	zero	pass	mubi_true	1017	1			T1	1		T21	2		T35	5
gen	non_zero_bins[0]	pass	mubi_false	428	1			T21	2		T8	2		T50	1
gen	non_zero_bins[0]	pass	mubi_true	443	1			T21	1		T35	6		T36	1
gen	non_zero_bins[1]	pass	mubi_false	339	1			T35	3		T22	3		T23	7
gen	non_zero_bins[1]	pass	mubi_true	321	1			T21	1		T35	1		T22	1
gen	zero	fail	mubi_false	23	1			T17	1		T74	1		T75	1
gen	zero	pass	mubi_false	1875	1			T1	1		T4	1		T21	4
gen	zero	pass	mubi_true	421	1			T2	2		T14	1		T36	1
res	non_zero_bins[0]	pass	mubi_false	188	1			T22	1		T23	2		T138	1
res	non_zero_bins[0]	pass	mubi_true	153	1			T35	1		T36	1		T9	3
res	non_zero_bins[1]	pass	mubi_false	131	1			T21	1		T22	1		T144	3
res	non_zero_bins[1]	pass	mubi_true	135	1			T21	1		T35	2		T8	4
res	zero	fail	mubi_false	8	1			T149	1		T234	1		T235	1
res	zero	pass	mubi_false	76	1			T23	1		T24	2		T143	2
res	zero	pass	mubi_true	77	1			T22	2		T23	1		T24	1
ins	non_zero_bins[0]	pass	mubi_false	540	1			T21	3		T35	4		T8	1
ins	non_zero_bins[0]	pass	mubi_true	535	1			T21	1		T35	4		T50	1
ins	non_zero_bins[1]	pass	mubi_false	363	1			T21	1		T35	3		T22	1
ins	non_zero_bins[1]	pass	mubi_true	375	1			T35	3		T36	1		T50	1
ins	zero	fail	mubi_false	6	1			T109	1		T110	1		T111	1
ins	zero	fail	mubi_true	1	1			T236	1		-	-		-	-
ins	zero	pass	mubi_false	1972	1			T1	1		T4	1		T14	1
ins	zero	pass	mubi_true	418	1			T2	2		T14	1		T22	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded