Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	224080234	9779170	0	0
boot_gen_cmd_rd_A	224080234	67249	0	0
boot_ins_cmd_rd_A	224080234	78415	0	0
ctrl_rd_A	224080234	68191	0	0
err_code_test_rd_A	224080234	78246	0	0
intr_enable_rd_A	224080234	74749	0	0
max_num_reqs_between_reseeds_rd_A	224080234	70065	0	0
regwen_rd_A	224080234	80192	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	9779170	0	0
T10	2065	0	0	0
T22	206868	115972	0	0
T23	566801	193907	0	0
T24	0	85018	0	0
T28	2297	0	0	0
T30	777	0	0	0
T67	1804	0	0	0
T86	2674	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	0	432367	0	0
T144	0	79114	0	0
T145	0	315327	0	0
T146	5997	0	0	0
T153	0	58290	0	0
T155	0	232973	0	0
T188	0	106310	0	0
T189	0	114190	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	67249	0	0
T23	566801	5631	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	12443	0	0
T144	0	2309	0	0
T146	5997	0	0	0
T188	0	3136	0	0
T189	0	3376	0	0
T190	0	3846	0	0
T191	0	8826	0	0
T192	0	2338	0	0
T193	0	3420	0	0
T194	0	5332	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	78415	0	0
T23	566801	6473	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	14210	0	0
T144	0	2695	0	0
T146	5997	0	0	0
T188	0	3887	0	0
T189	0	3707	0	0
T190	0	4687	0	0
T191	0	10571	0	0
T192	0	2339	0	0
T193	0	3829	0	0
T194	0	5638	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	68191	0	0
T23	566801	5520	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	5	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	12428	0	0
T144	0	2304	0	0
T146	5997	0	0	0
T159	0	2	0	0
T188	0	2976	0	0
T189	0	3075	0	0
T190	0	4371	0	0
T191	0	9194	0	0
T195	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	78246	0	0
T23	566801	6310	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	14894	0	0
T144	0	2633	0	0
T146	5997	0	0	0
T188	0	3662	0	0
T189	0	3462	0	0
T190	0	4867	0	0
T191	0	10166	0	0
T192	0	2742	0	0
T193	0	4022	0	0
T194	0	5625	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	74749	0	0
T23	566801	6201	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	13443	0	0
T144	0	2554	0	0
T146	5997	0	0	0
T154	0	33	0	0
T188	0	3492	0	0
T189	0	3253	0	0
T190	0	4368	0	0
T191	0	9069	0	0
T192	0	2585	0	0
T196	0	48	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	70065	0	0
T23	566801	5357	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	12832	0	0
T144	0	2434	0	0
T146	5997	0	0	0
T188	0	3129	0	0
T189	0	3003	0	0
T190	0	4129	0	0
T191	0	9170	0	0
T192	0	2520	0	0
T193	0	3408	0	0
T194	0	5169	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224080234	80192	0	0
T23	566801	6400	0	0
T24	139687	0	0	0
T30	777	0	0	0
T31	4257	0	0	0
T67	1804	0	0	0
T71	2055	0	0	0
T129	1307	0	0	0
T138	2908	0	0	0
T143	124070	14329	0	0
T144	0	2593	0	0
T146	5997	0	0	0
T188	0	3515	0	0
T189	0	3778	0	0
T190	0	4767	0	0
T191	0	10688	0	0
T192	0	2827	0	0
T193	0	4077	0	0
T194	0	6104	0	0