Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	143	1			T1	1		T27	1		T22	1
auto_req_mode	136	1			T2	1		T10	1		T25	1
sw_mode	2912	1			T3	1		T21	1		T5	66

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

305

1

T1

1

T3

1

T27

1

single

86

1

T2

1

T54

1

T134

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1124	1			T1	1		T2	1		T3	1
auto[2]	109	1			T193	1		T136	1		T134	1
auto[3]	45	1			T138	7		T263	1		T264	1
auto[4]	165	1			T10	1		T175	1		T265	1
auto[5]	96	1			T26	1		T266	13		T267	1
auto[6]	170	1			T31	1		T198	32		T210	7
auto[7]	1482	1			T5	66		T23	60		T25	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	93	1			T1	1		T27	1		T22	1
auto[1]	auto_req_mode	79	1			T2	1		T124	1		T35	1
auto[1]	sw_mode	952	1			T3	1		T21	1		T38	1
auto[2]	boot_req_mode	6	1			T193	1		T134	1		T268	1
auto[2]	auto_req_mode	6	1			T136	1		T269	1		T270	1
auto[2]	sw_mode	97	1			T196	26		T271	1		T272	1
auto[3]	boot_req_mode	3	1			T273	1		T274	1		T275	1
auto[3]	auto_req_mode	3	1			T264	1		T276	1		T277	1
auto[3]	sw_mode	39	1			T138	7		T263	1		T208	9
auto[4]	boot_req_mode	6	1			T265	1		T278	1		T279	1
auto[4]	auto_req_mode	4	1			T10	1		T280	1		T281	1
auto[4]	sw_mode	155	1			T175	1		T181	1		T282	1
auto[5]	boot_req_mode	5	1			T26	1		T283	1		T284	1
auto[5]	auto_req_mode	4	1			T267	1		T285	1		T286	1
auto[5]	sw_mode	87	1			T266	13		T287	1		T288	1
auto[6]	boot_req_mode	1	1			T31	1		-	-		-	-
auto[6]	auto_req_mode	1	1			T289	1		-	-		-	-
auto[6]	sw_mode	168	1			T198	32		T210	7		T206	14
auto[7]	boot_req_mode	29	1			T184	1		T190	1		T192	1
auto[7]	auto_req_mode	39	1			T25	1		T28	1		T12	1
auto[7]	sw_mode	1414	1			T5	66		T23	60		T24	54