Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
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Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_hw_cmd_sts_cg 100.00 1 100 1 64 64




Group Instance : edn_hw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_hw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 5 0 5 100.00


Variables for Group Instance edn_hw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 4 0 4 100.00 100 1 1 0
cp_auto_mode 2 0 2 100.00 100 1 1 0
cp_boot_mode 2 0 2 100.00 100 1 1 0
cp_cmd_ack 2 0 2 100.00 100 1 1 0
cp_cmd_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance edn_hw_cmd_sts_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_acmd_boot_mode 3 0 3 100.00 100 1 1 0
cr_acmd_auto_mode 2 0 2 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[UPD] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 15 1 T99 1 T111 1 T100 2
auto[RES] 6 1 T11 1 T17 1 T141 1
auto[GEN] 33 1 T18 1 T149 1 T142 1
auto[UNI] 13 1 T18 1 T111 1 T112 1



Summary for Variable cp_auto_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_auto_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_auto_mode 77 1 T11 1 T17 1 T18 1
auto_mode 23 1 T11 1 T17 1 T18 1



Summary for Variable cp_boot_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_boot_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_boot_mode 64 1 T11 2 T17 2 T18 2
boot_mode 36 1 T99 1 T111 2 T92 1



Summary for Variable cp_cmd_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 48 1 T11 1 T17 1 T18 1
ack 52 1 T11 1 T17 1 T18 1



Summary for Variable cp_cmd_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
success 49 1 T11 1 T17 1 T18 1
error 51 1 T11 1 T17 1 T18 1



Summary for Cross cr_acmd_boot_mode

Samples crossed: cp_acmd cp_boot_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
cp_acmdcp_boot_modeCOUNTSTATUS
[auto[INV]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[UPD]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_boot_mode , boot_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_boot_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] boot_mode 15 1 T99 1 T111 1 T100 2
auto[GEN] boot_mode 10 1 T92 1 T93 1 T94 1
auto[UNI] boot_mode 10 1 T111 1 T112 1 T113 1


User Defined Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_boot_mode 0 Excluded
not_valid_boot_commands 0 Excluded



Summary for Cross cr_acmd_auto_mode

Samples crossed: cp_acmd cp_auto_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
cp_acmdcp_auto_modeCOUNTSTATUS
[auto[INV]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[UPD]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_auto_mode , auto_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_auto_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] auto_mode 6 1 T11 1 T17 1 T141 1
auto[GEN] auto_mode 17 1 T18 1 T149 1 T142 1


User Defined Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_auto_mode 0 Excluded
not_valid_boot_commands 0 Excluded

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