Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	696568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5771335

1

T1

4

T2

52

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1702530	1			T1	2		T2	49		T3	62
values[0x0]	2203739	1			T1	3		T2	28		T3	13
values[0x1]	2561634	1			T1	2		T2	27		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6127145

1

T1

4

T2

70

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25268	1			T21	1		T5	942		T38	1
valid_sources[0x01]	26243	1			T5	899		T6	4		T37	1
valid_sources[0x02]	25922	1			T5	908		T38	1		T6	1
valid_sources[0x03]	23794	1			T5	918		T6	1		T23	616
valid_sources[0x04]	26489	1			T21	3		T5	907		T37	1
valid_sources[0x05]	26342	1			T5	920		T6	2		T37	1
valid_sources[0x06]	25495	1			T5	954		T38	1		T6	1
valid_sources[0x07]	27074	1			T5	963		T6	3		T37	4
valid_sources[0x08]	25332	1			T5	923		T6	4		T23	555
valid_sources[0x09]	26962	1			T5	920		T6	1		T37	2
valid_sources[0x0a]	25828	1			T5	898		T6	3		T37	2
valid_sources[0x0b]	26690	1			T5	850		T6	2		T37	1
valid_sources[0x0c]	24824	1			T5	869		T23	601		T46	1
valid_sources[0x0d]	26547	1			T21	1		T5	1012		T6	3
valid_sources[0x0e]	24070	1			T21	1		T5	889		T6	3
valid_sources[0x0f]	24210	1			T21	1		T5	885		T6	1
valid_sources[0x10]	24945	1			T5	847		T6	2		T37	2
valid_sources[0x11]	25444	1			T5	894		T6	4		T23	577
valid_sources[0x12]	26000	1			T1	1		T5	971		T6	2
valid_sources[0x13]	25327	1			T5	916		T6	3		T37	1
valid_sources[0x14]	23714	1			T22	1		T5	864		T6	2
valid_sources[0x15]	25334	1			T5	876		T37	3		T23	579
valid_sources[0x16]	23640	1			T5	966		T23	554		T14	2
valid_sources[0x17]	26529	1			T5	909		T6	1		T23	508
valid_sources[0x18]	28199	1			T21	1		T5	914		T6	1
valid_sources[0x19]	24885	1			T4	4		T5	960		T38	1
valid_sources[0x1a]	25781	1			T5	907		T37	3		T23	590
valid_sources[0x1b]	25744	1			T1	1		T5	901		T37	5
valid_sources[0x1c]	24936	1			T5	906		T6	1		T23	515
valid_sources[0x1d]	24794	1			T5	925		T23	512		T14	4
valid_sources[0x1e]	26343	1			T5	925		T37	1		T23	605
valid_sources[0x1f]	26042	1			T5	924		T38	1		T6	2
valid_sources[0x20]	25454	1			T5	861		T6	2		T37	4
valid_sources[0x21]	26136	1			T5	858		T38	1		T23	574
valid_sources[0x22]	24259	1			T5	936		T6	3		T37	5
valid_sources[0x23]	25423	1			T5	931		T6	2		T37	1
valid_sources[0x24]	24320	1			T5	878		T6	2		T52	2
valid_sources[0x25]	25384	1			T5	898		T6	1		T37	2
valid_sources[0x26]	26529	1			T5	940		T6	1		T37	3
valid_sources[0x27]	27564	1			T5	936		T6	1		T23	567
valid_sources[0x28]	25226	1			T5	790		T38	1		T37	2
valid_sources[0x29]	24789	1			T5	914		T6	2		T37	4
valid_sources[0x2a]	24034	1			T5	895		T37	2		T23	531
valid_sources[0x2b]	24429	1			T5	925		T6	2		T37	1
valid_sources[0x2c]	26090	1			T4	1		T5	902		T6	2
valid_sources[0x2d]	25663	1			T5	894		T6	1		T23	577
valid_sources[0x2e]	24885	1			T1	1		T5	918		T6	1
valid_sources[0x2f]	25175	1			T5	896		T37	7		T23	529
valid_sources[0x30]	24707	1			T5	898		T6	3		T23	543
valid_sources[0x31]	24639	1			T5	909		T6	1		T37	1
valid_sources[0x32]	23990	1			T21	1		T5	922		T6	1
valid_sources[0x33]	26611	1			T5	951		T37	9		T23	550
valid_sources[0x34]	24701	1			T22	2		T5	935		T37	5
valid_sources[0x35]	24838	1			T5	929		T6	1		T23	597
valid_sources[0x36]	25398	1			T5	897		T37	6		T23	596
valid_sources[0x37]	25191	1			T5	918		T6	2		T23	560
valid_sources[0x38]	23509	1			T4	2		T5	944		T38	2
valid_sources[0x39]	25324	1			T1	1		T22	1		T5	910
valid_sources[0x3a]	26368	1			T5	908		T6	2		T37	3
valid_sources[0x3b]	25704	1			T5	851		T6	1		T37	5
valid_sources[0x3c]	24526	1			T5	935		T6	1		T37	4
valid_sources[0x3d]	25800	1			T5	915		T23	599		T14	2
valid_sources[0x3e]	24694	1			T5	919		T6	2		T37	3
valid_sources[0x3f]	23918	1			T5	928		T37	2		T23	543
valid_sources[0x40]	24511	1			T5	864		T6	1		T37	1
valid_sources[0x41]	25338	1			T5	899		T37	1		T23	563
valid_sources[0x42]	25958	1			T5	990		T6	2		T37	3
valid_sources[0x43]	24676	1			T5	885		T6	1		T37	4
valid_sources[0x44]	23836	1			T5	911		T37	2		T23	525
valid_sources[0x45]	25560	1			T21	1		T5	966		T6	1
valid_sources[0x46]	24638	1			T5	946		T37	2		T23	598
valid_sources[0x47]	22271	1			T5	933		T37	3		T23	519
valid_sources[0x48]	24023	1			T5	898		T23	547		T14	7
valid_sources[0x49]	26097	1			T5	921		T6	2		T37	3
valid_sources[0x4a]	24220	1			T5	1003		T6	1		T37	2
valid_sources[0x4b]	24564	1			T5	917		T38	1		T37	5
valid_sources[0x4c]	26132	1			T5	906		T6	1		T37	2
valid_sources[0x4d]	25670	1			T5	940		T6	1		T23	521
valid_sources[0x4e]	24345	1			T5	900		T37	1		T23	547
valid_sources[0x4f]	28297	1			T5	987		T6	1		T52	7
valid_sources[0x50]	23844	1			T5	913		T6	1		T37	6
valid_sources[0x51]	24890	1			T5	876		T6	1		T23	502
valid_sources[0x52]	26885	1			T5	878		T6	1		T23	665
valid_sources[0x53]	25687	1			T5	928		T6	1		T23	510
valid_sources[0x54]	25589	1			T5	938		T6	2		T23	607
valid_sources[0x55]	26238	1			T5	870		T37	3		T23	585
valid_sources[0x56]	24896	1			T21	1		T4	3		T5	947
valid_sources[0x57]	25033	1			T5	851		T6	1		T37	6
valid_sources[0x58]	24818	1			T5	909		T6	1		T23	623
valid_sources[0x59]	25580	1			T5	922		T6	1		T37	2
valid_sources[0x5a]	27322	1			T5	905		T37	3		T23	487
valid_sources[0x5b]	25274	1			T5	870		T38	1		T37	2
valid_sources[0x5c]	26255	1			T4	1		T5	934		T6	4
valid_sources[0x5d]	24790	1			T5	910		T37	4		T23	593
valid_sources[0x5e]	24229	1			T5	893		T6	3		T23	523
valid_sources[0x5f]	25675	1			T5	899		T6	1		T37	4
valid_sources[0x60]	25720	1			T5	887		T38	1		T6	1
valid_sources[0x61]	25768	1			T5	874		T23	485		T14	1
valid_sources[0x62]	27244	1			T5	950		T38	3		T6	1
valid_sources[0x63]	26281	1			T5	889		T6	2		T23	527
valid_sources[0x64]	27127	1			T5	883		T6	1		T37	7
valid_sources[0x65]	25053	1			T5	931		T37	2		T23	578
valid_sources[0x66]	24233	1			T5	966		T6	6		T23	563
valid_sources[0x67]	25509	1			T5	908		T6	1		T37	3
valid_sources[0x68]	25765	1			T2	104		T21	1		T5	923
valid_sources[0x69]	25877	1			T5	898		T6	2		T37	4
valid_sources[0x6a]	27182	1			T5	918		T6	1		T37	1
valid_sources[0x6b]	25336	1			T5	902		T6	3		T37	1
valid_sources[0x6c]	25265	1			T5	974		T6	3		T37	4
valid_sources[0x6d]	24022	1			T5	933		T37	6		T23	536
valid_sources[0x6e]	24272	1			T5	931		T6	1		T37	2
valid_sources[0x6f]	25556	1			T5	906		T6	3		T37	2
valid_sources[0x70]	25374	1			T5	960		T52	1		T23	512
valid_sources[0x71]	25927	1			T5	941		T6	1		T23	554
valid_sources[0x72]	25370	1			T5	874		T37	1		T52	1
valid_sources[0x73]	25741	1			T5	956		T6	1		T37	2
valid_sources[0x74]	24497	1			T5	861		T6	1		T37	2
valid_sources[0x75]	25649	1			T5	917		T6	1		T37	2
valid_sources[0x76]	23891	1			T5	916		T6	2		T37	1
valid_sources[0x77]	27233	1			T5	886		T6	3		T37	3
valid_sources[0x78]	25097	1			T5	915		T37	1		T23	535
valid_sources[0x79]	25112	1			T5	943		T37	1		T23	574
valid_sources[0x7a]	25656	1			T5	876		T6	3		T52	9
valid_sources[0x7b]	24759	1			T4	6		T5	919		T6	1
valid_sources[0x7c]	25397	1			T5	969		T6	2		T23	490
valid_sources[0x7d]	24830	1			T21	1		T5	873		T38	2
valid_sources[0x7e]	26165	1			T5	928		T6	2		T37	1
valid_sources[0x7f]	25757	1			T1	1		T5	922		T37	2
valid_sources[0x80]	24566	1			T5	878		T6	1		T37	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1453653

1

T1

1

T2

3

T3

2

values[0x0]

all_enables

biggest_size

2160128

1

T1

3

T2

25

T3

12

values[0x1]

all_enables

biggest_size

2157554

1

T2

24

T3

12

T21

3