Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
67.19 67.19 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 67.19 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
67.19 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 21 31 59.62


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 21 31 59.62 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2595 1 T2 4 T3 2 T5 40
non_zero_bins[1] 1833 1 T2 3 T3 1 T5 27
zero 8462 1 T1 4 T2 1 T3 1



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 537 1 T3 1 T5 12 T36 1
uni 3589 1 T2 1 T3 1 T21 1
gen 3847 1 T1 2 T2 4 T3 1
res 804 1 T2 2 T5 7 T37 1
ins 4113 1 T1 2 T2 1 T3 1



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 8644 1 T1 2 T2 4 T3 2
mubi_true 4246 1 T1 2 T2 4 T3 2



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 50 1 T11 1 T17 1 T18 1
pass 12840 1 T1 4 T2 8 T3 4



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 21 31 59.62 21
Automatically Generated Cross Bins 52 21 31 59.62 21
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 4


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[uni] [zero] [fail] [mubi_true] 0 1 1
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 108 1 T5 5 T6 1 T23 2
upd non_zero_bins[0] pass mubi_true 122 1 T3 1 T5 3 T23 2
upd non_zero_bins[1] pass mubi_false 89 1 T23 1 T24 1 T241 1
upd non_zero_bins[1] pass mubi_true 100 1 T5 1 T36 1 T23 2
upd zero pass mubi_false 64 1 T5 2 T194 1 T135 1
upd zero pass mubi_true 54 1 T5 1 T23 1 T24 1
uni zero fail mubi_false 10 1 T111 1 T112 1 T113 1
uni zero pass mubi_false 2592 1 T2 1 T3 1 T5 54
uni zero pass mubi_true 987 1 T21 1 T5 22 T38 1
gen non_zero_bins[0] pass mubi_false 411 1 T3 1 T5 4 T6 1
gen non_zero_bins[0] pass mubi_true 533 1 T2 1 T5 6 T23 10
gen non_zero_bins[1] pass mubi_false 314 1 T2 3 T5 6 T23 3
gen non_zero_bins[1] pass mubi_true 346 1 T5 6 T36 1 T23 4
gen zero fail mubi_false 27 1 T18 1 T149 1 T142 1
gen zero pass mubi_false 1822 1 T21 1 T22 1 T5 40
gen zero pass mubi_true 394 1 T1 2 T4 1 T27 1
res non_zero_bins[0] pass mubi_false 178 1 T5 1 T23 4 T24 1
res non_zero_bins[0] pass mubi_true 172 1 T2 2 T5 2 T37 1
res non_zero_bins[1] pass mubi_false 120 1 T5 1 T23 2 T138 1
res non_zero_bins[1] pass mubi_true 133 1 T5 1 T23 2 T46 1
res zero fail mubi_false 6 1 T11 1 T17 1 T141 1
res zero pass mubi_false 97 1 T5 1 T25 2 T24 3
res zero pass mubi_true 98 1 T5 1 T24 1 T124 2
ins non_zero_bins[0] pass mubi_false 550 1 T5 7 T6 1 T37 1
ins non_zero_bins[0] pass mubi_true 521 1 T2 1 T5 12 T23 15
ins non_zero_bins[1] pass mubi_false 367 1 T5 5 T6 2 T37 1
ins non_zero_bins[1] pass mubi_true 364 1 T3 1 T5 7 T37 1
ins zero fail mubi_false 6 1 T99 1 T100 1 T242 1
ins zero fail mubi_true 1 1 T101 1 - - - -
ins zero pass mubi_false 1883 1 T1 2 T21 1 T5 41
ins zero pass mubi_true 421 1 T4 1 T27 2 T22 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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