Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	228318187	10193226	0	0
boot_gen_cmd_rd_A	228318187	75721	0	0
boot_ins_cmd_rd_A	228318187	87409	0	0
ctrl_rd_A	228318187	76186	0	0
err_code_test_rd_A	228318187	86261	0	0
intr_enable_rd_A	228318187	83361	0	0
max_num_reqs_between_reseeds_rd_A	228318187	76855	0	0
regwen_rd_A	228318187	87865	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	10193226	0	0
T5	686923	383875	0	0
T6	7926	0	0	0
T10	1923	0	0	0
T14	37440	0	0	0
T23	610384	226433	0	0
T24	0	236763	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T135	0	165005	0	0
T196	0	54797	0	0
T197	0	444877	0	0
T198	0	135655	0	0
T199	0	178559	0	0
T200	0	20962	0	0
T201	0	312077	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	75721	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3694	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T135	0	2735	0	0
T196	0	1696	0	0
T198	0	3885	0	0
T199	0	2697	0	0
T200	0	580	0	0
T202	0	4231	0	0
T203	0	207	0	0
T204	0	6275	0	0
T205	0	9348	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	87409	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3858	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T135	0	3021	0	0
T196	0	1786	0	0
T198	0	4168	0	0
T199	0	3493	0	0
T200	0	671	0	0
T202	0	4874	0	0
T203	0	253	0	0
T204	0	6968	0	0
T205	0	11417	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	76186	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3454	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T115	0	4	0	0
T135	0	2798	0	0
T196	0	1433	0	0
T198	0	3700	0	0
T199	0	2878	0	0
T200	0	669	0	0
T206	0	3	0	0
T207	0	8	0	0
T208	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	86261	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3988	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T135	0	2941	0	0
T196	0	1774	0	0
T198	0	4120	0	0
T199	0	3020	0	0
T200	0	682	0	0
T202	0	4681	0	0
T203	0	297	0	0
T204	0	7059	0	0
T205	0	10815	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	83361	0	0
T7	2736	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3839	0	0
T37	17908	48	0	0
T46	4590	0	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T135	0	2831	0	0
T138	0	49	0	0
T196	0	1935	0	0
T198	0	3853	0	0
T199	0	2914	0	0
T206	0	25	0	0
T209	0	5	0	0
T210	0	20	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	76855	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3670	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T135	0	2535	0	0
T196	0	1572	0	0
T198	0	3848	0	0
T199	0	2518	0	0
T200	0	591	0	0
T202	0	4149	0	0
T203	0	220	0	0
T204	0	6095	0	0
T205	0	9585	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228318187	87865	0	0
T7	2736	0	0	0
T8	1246	0	0	0
T10	1923	0	0	0
T11	2113	0	0	0
T14	37440	0	0	0
T15	892	0	0	0
T23	610384	3929	0	0
T30	658	0	0	0
T46	4590	0	0	0
T47	1746	0	0	0
T135	0	3214	0	0
T196	0	1668	0	0
T198	0	4335	0	0
T199	0	3210	0	0
T200	0	658	0	0
T202	0	4431	0	0
T203	0	241	0	0
T204	0	6919	0	0
T205	0	11209	0	0