Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T21
DataWait	75	Covered	T2,T3,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T150,T151,T152
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T21
DataWait->AckPls	80	Covered	T2,T3,T21
DataWait->Disabled	107	Covered	T61,T153,T104
DataWait->Error	99	Covered	T7,T98,T87
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T21
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T8

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T21
Idle	-	1	0	-	Covered	T2,T3,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T21
DataWait	-	-	-	0	Covered	T2,T3,T21
AckPls	-	-	-	-	Covered	T2,T3,T21
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T4,T14,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1594772011	949226	0	0
FpvSecCmErrorStEscalate_A	1594772011	955197	0	0
u_state_regs_A	1594739036	1593664298	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1594772011	949226	0	0
T4	8316	4479	0	0
T5	4808461	0	0	0
T6	55482	0	0	0
T7	0	7944	0	0
T8	0	4270	0	0
T14	0	69706	0	0
T15	0	2688	0	0
T16	0	4466	0	0
T22	4438	0	0	0
T27	8470	0	0	0
T30	0	1680	0	0
T36	15001	0	0	0
T37	125356	0	0	0
T38	13209	0	0	0
T50	0	2617	0	0
T52	11739	0	0	0
T53	8218	0	0	0
T98	0	7875	0	0
T114	0	1595	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1594772011	955197	0	0
T4	8316	4486	0	0
T5	4808461	0	0	0
T6	55482	0	0	0
T7	0	7951	0	0
T8	0	4277	0	0
T14	0	70966	0	0
T15	0	2695	0	0
T16	0	4473	0	0
T22	4438	0	0	0
T27	8470	0	0	0
T30	0	1687	0	0
T36	15001	0	0	0
T37	125356	0	0	0
T38	13209	0	0	0
T50	0	2624	0	0
T52	11739	0	0	0
T53	8218	0	0	0
T98	0	7882	0	0
T114	0	1602	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1594739036	1593664298	0	0
T1	5425	5075	0	0
T2	30352	29764	0	0
T3	16744	16107	0	0
T4	8139	6914	0	0
T5	4808461	4808370	0	0
T21	12551	11900	0	0
T22	4438	4018	0	0
T27	8470	7840	0	0
T36	15001	14609	0	0
T38	13209	12677	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T21
DataWait	75	Covered	T2,T3,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T21
DataWait->AckPls	80	Covered	T2,T3,T21
DataWait->Disabled	107	Covered	T104,T155,T156
DataWait->Error	99	Covered	T98,T87,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T14,T157,T158
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T21
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T15,T8,T30

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T21
Idle	-	1	0	-	Covered	T2,T3,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T21
DataWait	-	-	-	0	Covered	T2,T3,T21
AckPls	-	-	-	-	Covered	T2,T3,T21
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T4,T14,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	133718	0	0
FpvSecCmErrorStEscalate_A	227824573	134571	0	0
u_state_regs_A	227791598	227638064	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	133718	0	0
T4	1188	597	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1092	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	331	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	185	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	134571	0	0
T4	1188	598	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1093	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	332	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	186	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227791598	227638064	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1011	836	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T25,T26
DataWait	75	Covered	T10,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T25,T26
DataWait->AckPls	80	Covered	T10,T25,T26
DataWait->Disabled	107	Covered	T61,T105,T63
DataWait->Error	99	Covered	T96,T67,T159
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T25,T26
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T25,T26
Idle	-	1	0	-	Covered	T10,T25,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T25,T26
DataWait	-	-	-	0	Covered	T10,T25,T26
AckPls	-	-	-	-	Covered	T10,T25,T26
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T10,T25
DataWait	75	Covered	T27,T10,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T10,T25
DataWait->AckPls	80	Covered	T27,T10,T25
DataWait->Disabled	107	Covered	T62,T160,T161
DataWait->Error	99	Covered	T7,T162,T83
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T10,T7
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T15,T8,T30

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T10,T25
Idle	-	1	0	-	Covered	T27,T10,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T10,T25
DataWait	-	-	-	0	Covered	T27,T10,T7
AckPls	-	-	-	-	Covered	T27,T10,T25
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T10,T26
DataWait	75	Covered	T22,T10,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T10,T26
DataWait->AckPls	80	Covered	T22,T10,T26
DataWait->Disabled	107	Covered	T163,T164,T165
DataWait->Error	99	Covered	T148,T166,T167
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T10,T26
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T10,T26
Idle	-	1	0	-	Covered	T22,T10,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T10,T26
DataWait	-	-	-	0	Covered	T22,T10,T26
AckPls	-	-	-	-	Covered	T22,T10,T26
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T28,T12
DataWait	75	Covered	T1,T28,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T28,T12
DataWait->AckPls	80	Covered	T1,T28,T12
DataWait->Disabled	107	Covered	T35,T168,T106
DataWait->Error	99	Covered	T40,T169
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T28,T12
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T28,T12
Idle	-	1	0	-	Covered	T1,T28,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T28,T12
DataWait	-	-	-	0	Covered	T1,T28,T12
AckPls	-	-	-	-	Covered	T1,T28,T12
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T29,T31
DataWait	75	Covered	T8,T28,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T150
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T29,T31
DataWait->AckPls	80	Covered	T28,T29,T31
DataWait->Disabled	107	Covered	T153,T77,T91
DataWait->Error	99	Covered	T8,T70,T170
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T28,T29
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T30

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T28,T29,T31
Idle	-	1	0	-	Covered	T8,T28,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T28,T29,T31
DataWait	-	-	-	0	Covered	T8,T28,T31
AckPls	-	-	-	-	Covered	T28,T29,T31
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T28,T31
DataWait	75	Covered	T30,T28,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T151,T152
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T28,T31
DataWait->AckPls	80	Covered	T30,T28,T31
DataWait->Disabled	107	Covered	T171,T172,T173
DataWait->Error	99	Covered	T174,T103
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T19,T20
EndPointClear->Disabled	107	Covered	T22,T132,T154
EndPointClear->Error	99	Covered	T4,T14,T9
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T28,T31
Idle->Disabled	107	Covered	T1,T4,T27
Idle->Error	99	Covered	T7,T15,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T28,T31
Idle	-	1	0	-	Covered	T30,T28,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T28,T31
DataWait	-	-	-	0	Covered	T28,T31,T34
AckPls	-	-	-	-	Covered	T30,T28,T31
Error	-	-	-	-	Covered	T4,T14,T7
default	-	-	-	-	Covered	T14,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T7
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	227824573	135918	0	0
FpvSecCmErrorStEscalate_A	227824573	136771	0	0
u_state_regs_A	227824573	227671039	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	135918	0	0
T4	1188	647	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1142	0	0
T8	0	610	0	0
T14	0	9958	0	0
T15	0	384	0	0
T16	0	638	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	240	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	381	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1125	0	0
T114	0	235	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	136771	0	0
T4	1188	648	0	0
T5	686923	0	0	0
T6	7926	0	0	0
T7	0	1143	0	0
T8	0	611	0	0
T14	0	10138	0	0
T15	0	385	0	0
T16	0	639	0	0
T22	634	0	0	0
T27	1210	0	0	0
T30	0	241	0	0
T36	2143	0	0	0
T37	17908	0	0	0
T38	1887	0	0	0
T50	0	382	0	0
T52	1677	0	0	0
T53	1174	0	0	0
T98	0	1126	0	0
T114	0	236	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227824573	227671039	0	0
T1	775	725	0	0
T2	4336	4252	0	0
T3	2392	2301	0	0
T4	1188	1013	0	0
T5	686923	686910	0	0
T21	1793	1700	0	0
T22	634	574	0	0
T27	1210	1120	0	0
T36	2143	2087	0	0
T38	1887	1811	0	0