Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	701343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5527401

1

T1

7

T2

53

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1663386	1			T1	30		T2	31		T3	152
values[0x0]	2110917	1			T1	3		T2	26		T3	10
values[0x1]	2454441	1			T1	4		T2	31		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350677	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5878067

1

T1

13

T2

61

T3

70

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25786	1			T2	1		T21	4		T19	1
valid_sources[0x01]	24781	1			T2	1		T22	582		T7	6
valid_sources[0x02]	22783	1			T21	2		T25	2		T22	533
valid_sources[0x03]	23934	1			T3	9		T21	2		T22	607
valid_sources[0x04]	23323	1			T2	1		T5	1		T29	1
valid_sources[0x05]	24341	1			T3	1		T29	1		T22	563
valid_sources[0x06]	24352	1			T9	2		T5	2		T22	608
valid_sources[0x07]	23470	1			T3	11		T9	1		T22	562
valid_sources[0x08]	24239	1			T3	1		T22	561		T23	440
valid_sources[0x09]	26776	1			T2	1		T21	1		T29	1
valid_sources[0x0a]	25812	1			T1	1		T9	2		T22	611
valid_sources[0x0b]	25457	1			T21	1		T25	1		T29	1
valid_sources[0x0c]	23171	1			T2	2		T25	1		T9	1
valid_sources[0x0d]	23862	1			T2	1		T3	9		T21	1
valid_sources[0x0e]	24881	1			T21	3		T25	1		T29	1
valid_sources[0x0f]	23697	1			T2	1		T9	1		T5	1
valid_sources[0x10]	24041	1			T1	1		T2	1		T9	3
valid_sources[0x11]	25375	1			T3	1		T21	3		T19	5
valid_sources[0x12]	24935	1			T2	2		T21	2		T25	1
valid_sources[0x13]	24506	1			T21	4		T25	1		T9	1
valid_sources[0x14]	24848	1			T25	1		T47	1		T22	536
valid_sources[0x15]	24036	1			T3	2		T21	1		T25	1
valid_sources[0x16]	25196	1			T3	5		T21	4		T25	1
valid_sources[0x17]	22912	1			T21	2		T19	3		T9	3
valid_sources[0x18]	24921	1			T21	7		T25	2		T22	565
valid_sources[0x19]	24355	1			T5	1		T29	1		T22	567
valid_sources[0x1a]	24358	1			T3	1		T21	2		T47	1
valid_sources[0x1b]	23690	1			T20	3		T29	1		T22	568
valid_sources[0x1c]	24072	1			T21	1		T5	1		T30	5
valid_sources[0x1d]	25014	1			T25	1		T29	3		T48	3
valid_sources[0x1e]	23629	1			T22	566		T23	163		T138	7
valid_sources[0x1f]	25292	1			T19	2		T29	3		T47	8
valid_sources[0x20]	24470	1			T25	2		T9	7		T29	1
valid_sources[0x21]	24215	1			T25	4		T9	3		T29	1
valid_sources[0x22]	23475	1			T1	1		T2	1		T21	1
valid_sources[0x23]	22566	1			T21	3		T29	2		T22	567
valid_sources[0x24]	24131	1			T2	1		T25	2		T5	1
valid_sources[0x25]	24014	1			T21	1		T25	1		T9	6
valid_sources[0x26]	24058	1			T3	2		T21	1		T29	2
valid_sources[0x27]	22846	1			T25	1		T22	596		T23	234
valid_sources[0x28]	24712	1			T2	1		T19	1		T22	524
valid_sources[0x29]	25372	1			T19	1		T25	1		T5	2
valid_sources[0x2a]	26052	1			T2	1		T25	1		T29	1
valid_sources[0x2b]	26000	1			T21	9		T25	1		T9	2
valid_sources[0x2c]	22764	1			T1	1		T9	1		T22	595
valid_sources[0x2d]	24686	1			T21	4		T22	584		T38	1
valid_sources[0x2e]	25313	1			T21	1		T19	2		T29	2
valid_sources[0x2f]	22569	1			T1	1		T9	4		T29	1
valid_sources[0x30]	23778	1			T21	4		T29	1		T22	562
valid_sources[0x31]	25269	1			T1	1		T5	1		T48	3
valid_sources[0x32]	25027	1			T21	1		T25	1		T48	1
valid_sources[0x33]	24055	1			T2	1		T22	548		T23	529
valid_sources[0x34]	23331	1			T2	2		T3	1		T21	2
valid_sources[0x35]	23525	1			T2	1		T9	1		T5	1
valid_sources[0x36]	23677	1			T19	3		T29	1		T22	552
valid_sources[0x37]	23244	1			T2	1		T9	1		T29	1
valid_sources[0x38]	24012	1			T21	3		T19	1		T9	3
valid_sources[0x39]	23235	1			T2	1		T5	1		T29	1
valid_sources[0x3a]	23247	1			T1	1		T2	2		T3	1
valid_sources[0x3b]	24322	1			T3	3		T48	1		T22	541
valid_sources[0x3c]	25167	1			T5	1		T29	1		T22	582
valid_sources[0x3d]	24276	1			T1	1		T3	4		T25	2
valid_sources[0x3e]	24836	1			T3	3		T25	1		T9	1
valid_sources[0x3f]	23465	1			T2	1		T3	4		T9	4
valid_sources[0x40]	25224	1			T3	2		T9	1		T5	1
valid_sources[0x41]	24384	1			T2	1		T3	1		T21	4
valid_sources[0x42]	24675	1			T1	1		T19	2		T9	3
valid_sources[0x43]	23440	1			T2	1		T22	568		T23	411
valid_sources[0x44]	23584	1			T1	2		T3	1		T21	4
valid_sources[0x45]	24768	1			T2	1		T21	3		T19	2
valid_sources[0x46]	24665	1			T21	1		T25	3		T29	1
valid_sources[0x47]	24924	1			T3	4		T25	1		T47	3
valid_sources[0x48]	24934	1			T21	1		T25	1		T29	3
valid_sources[0x49]	23795	1			T5	1		T47	1		T22	610
valid_sources[0x4a]	24005	1			T21	3		T29	1		T22	527
valid_sources[0x4b]	30855	1			T21	1		T25	3		T5	1
valid_sources[0x4c]	24900	1			T9	4		T22	547		T40	1
valid_sources[0x4d]	22411	1			T2	1		T3	2		T19	3
valid_sources[0x4e]	25141	1			T25	3		T9	2		T29	1
valid_sources[0x4f]	23025	1			T47	3		T22	559		T23	182
valid_sources[0x50]	26182	1			T2	1		T21	5		T9	5
valid_sources[0x51]	25070	1			T2	1		T22	613		T23	510
valid_sources[0x52]	24881	1			T2	1		T5	2		T48	1
valid_sources[0x53]	26382	1			T1	1		T3	1		T29	1
valid_sources[0x54]	24353	1			T9	1		T47	1		T48	1
valid_sources[0x55]	23941	1			T19	1		T25	1		T9	1
valid_sources[0x56]	23808	1			T29	1		T48	4		T22	576
valid_sources[0x57]	25937	1			T2	1		T3	3		T25	2
valid_sources[0x58]	24903	1			T3	2		T25	2		T29	2
valid_sources[0x59]	24237	1			T3	9		T29	7		T22	581
valid_sources[0x5a]	24586	1			T1	2		T2	1		T19	2
valid_sources[0x5b]	24652	1			T21	4		T22	615		T23	226
valid_sources[0x5c]	22247	1			T29	3		T47	3		T22	559
valid_sources[0x5d]	25537	1			T2	1		T3	1		T21	1
valid_sources[0x5e]	22642	1			T2	1		T22	583		T23	8
valid_sources[0x5f]	23560	1			T1	1		T25	1		T22	567
valid_sources[0x60]	24749	1			T22	552		T23	730		T138	2
valid_sources[0x61]	24985	1			T1	1		T2	1		T3	3
valid_sources[0x62]	22477	1			T21	3		T25	1		T22	613
valid_sources[0x63]	24713	1			T2	1		T3	1		T9	1
valid_sources[0x64]	24449	1			T21	1		T5	2		T29	2
valid_sources[0x65]	25699	1			T21	2		T25	1		T9	9
valid_sources[0x66]	23743	1			T29	2		T22	573		T23	296
valid_sources[0x67]	26041	1			T2	1		T4	20		T22	564
valid_sources[0x68]	24593	1			T3	5		T25	1		T5	1
valid_sources[0x69]	24934	1			T2	1		T25	2		T9	3
valid_sources[0x6a]	24998	1			T3	6		T19	6		T5	1
valid_sources[0x6b]	22188	1			T22	545		T23	56		T138	10
valid_sources[0x6c]	25183	1			T5	1		T29	1		T22	599
valid_sources[0x6d]	22518	1			T25	1		T22	567		T60	1
valid_sources[0x6e]	23286	1			T2	1		T19	4		T29	1
valid_sources[0x6f]	25204	1			T3	1		T9	9		T22	581
valid_sources[0x70]	24374	1			T2	1		T21	2		T9	6
valid_sources[0x71]	23286	1			T21	5		T9	4		T29	1
valid_sources[0x72]	23957	1			T25	1		T22	545		T23	136
valid_sources[0x73]	25028	1			T21	1		T9	2		T29	3
valid_sources[0x74]	27179	1			T1	1		T2	1		T9	1
valid_sources[0x75]	24424	1			T2	1		T29	1		T22	548
valid_sources[0x76]	30387	1			T5	1		T29	1		T22	594
valid_sources[0x77]	23478	1			T29	1		T22	558		T60	1
valid_sources[0x78]	24096	1			T25	2		T5	3		T29	1
valid_sources[0x79]	23013	1			T25	1		T22	586		T23	334
valid_sources[0x7a]	23855	1			T25	1		T48	1		T22	565
valid_sources[0x7b]	23946	1			T21	2		T5	1		T29	3
valid_sources[0x7c]	25533	1			T3	2		T19	1		T25	1
valid_sources[0x7d]	26038	1			T9	4		T22	607		T23	721
valid_sources[0x7e]	23600	1			T2	2		T19	2		T9	1
valid_sources[0x7f]	22900	1			T3	2		T9	4		T22	580
valid_sources[0x80]	24436	1			T21	2		T29	1		T22	564

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1393628

1

T1

4

T2

2

T3

5

values[0x0]

all_enables

biggest_size

2067281

1

T1

1

T2

23

T3

8

values[0x1]

all_enables

biggest_size

2066492

1

T1

2

T2

28

T3

10