Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
65.62 65.62 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 65.62 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
65.62 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 22 30 57.69


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 22 30 57.69 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2695 1 T2 5 T3 1 T21 2
non_zero_bins[1] 1998 1 T21 1 T26 1 T6 3
zero 9093 1 T1 3 T2 2 T21 1



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 559 1 T29 1 T22 10 T142 1
uni 3920 1 T1 1 T21 1 T19 1
gen 4099 1 T1 1 T2 3 T21 1
res 791 1 T2 2 T21 1 T26 1
ins 4417 1 T1 1 T2 2 T3 1



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 9379 1 T1 2 T2 6 T3 1
mubi_true 4407 1 T1 1 T2 1 T21 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 50 1 T13 1 T14 1 T15 1
pass 13736 1 T1 3 T2 7 T3 1



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 22 30 57.69 22
Automatically Generated Cross Bins 52 22 30 57.69 22
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[gen , res , ins] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 12


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[uni] [zero] [fail] [mubi_true] 0 1 1
[gen , res , ins] [zero] [fail] [mubi_true] -- -- 3


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 143 1 T29 1 T22 4 T23 1
upd non_zero_bins[0] pass mubi_true 122 1 T23 2 T138 1 T139 1
upd non_zero_bins[1] pass mubi_false 86 1 T22 3 T142 1 T23 3
upd non_zero_bins[1] pass mubi_true 85 1 T22 1 T23 3 T139 1
upd zero pass mubi_false 56 1 T23 1 T138 1 T24 1
upd zero pass mubi_true 67 1 T22 2 T23 2 T138 1
uni zero fail mubi_false 10 1 T13 1 T122 1 T123 1
uni zero pass mubi_false 2832 1 T21 1 T19 1 T26 2
uni zero pass mubi_true 1078 1 T1 1 T6 4 T22 16
gen non_zero_bins[0] pass mubi_false 452 1 T2 1 T21 1 T6 1
gen non_zero_bins[0] pass mubi_true 463 1 T9 2 T22 7 T23 7
gen non_zero_bins[1] pass mubi_false 378 1 T6 1 T241 1 T22 2
gen non_zero_bins[1] pass mubi_true 413 1 T26 1 T6 1 T22 2
gen zero fail mubi_false 29 1 T15 1 T102 1 T103 1
gen zero pass mubi_false 1965 1 T1 1 T2 2 T4 1
gen zero pass mubi_true 399 1 T19 1 T20 2 T26 1
res non_zero_bins[0] pass mubi_false 209 1 T2 2 T26 1 T9 2
res non_zero_bins[0] pass mubi_true 182 1 T22 2 T23 3 T53 2
res non_zero_bins[1] pass mubi_false 119 1 T21 1 T22 1 T23 1
res non_zero_bins[1] pass mubi_true 141 1 T22 1 T60 1 T23 3
res zero fail mubi_false 5 1 T242 1 T174 1 T243 1
res zero pass mubi_false 70 1 T22 2 T23 1 T31 1
res zero pass mubi_true 65 1 T22 1 T23 1 T133 2
ins non_zero_bins[0] pass mubi_false 560 1 T2 1 T3 1 T19 1
ins non_zero_bins[0] pass mubi_true 564 1 T2 1 T21 1 T6 1
ins non_zero_bins[1] pass mubi_false 382 1 T6 1 T29 1 T47 1
ins non_zero_bins[1] pass mubi_true 394 1 T22 6 T23 12 T138 2
ins zero fail mubi_false 6 1 T14 1 T106 1 T107 1
ins zero pass mubi_false 2077 1 T1 1 T19 1 T20 2
ins zero pass mubi_true 434 1 T28 2 T4 1 T30 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%