Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	208086071	9801894	0	0
boot_gen_cmd_rd_A	208086071	43001	0	0
boot_ins_cmd_rd_A	208086071	49484	0	0
ctrl_rd_A	208086071	42966	0	0
err_code_test_rd_A	208086071	49221	0	0
intr_enable_rd_A	208086071	49854	0	0
max_num_reqs_between_reseeds_rd_A	208086071	43911	0	0
regwen_rd_A	208086071	50466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	9801894	0	0
T7	2558	0	0	0
T22	425067	235850	0	0
T23	306818	128658	0	0
T24	0	131386	0	0
T38	1227	0	0	0
T40	827	0	0	0
T54	0	347427	0	0
T60	2672	0	0	0
T116	839	0	0	0
T140	0	295831	0	0
T141	1513	0	0	0
T142	2069	0	0	0
T184	0	47250	0	0
T185	0	130575	0	0
T186	0	306175	0	0
T187	0	392310	0	0
T188	0	69133	0	0
T189	1593	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	43001	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	602	0	0
T185	0	3730	0	0
T190	0	2613	0	0
T191	0	2689	0	0
T192	0	10227	0	0
T193	0	6798	0	0
T194	0	10110	0	0
T195	0	5571	0	0
T196	0	79	0	0
T197	0	22	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	49484	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	763	0	0
T185	0	4322	0	0
T190	0	2698	0	0
T191	0	3419	0	0
T192	0	11822	0	0
T193	0	7734	0	0
T194	0	12092	0	0
T195	0	5951	0	0
T196	0	75	0	0
T198	0	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	42966	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T63	0	4	0	0
T82	1947	0	0	0
T111	710	0	0	0
T126	0	3	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	706	0	0
T185	0	3769	0	0
T190	0	2594	0	0
T191	0	3079	0	0
T199	0	2	0	0
T200	0	1	0	0
T201	0	3	0	0
T202	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	49221	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	758	0	0
T185	0	4319	0	0
T190	0	3043	0	0
T191	0	3565	0	0
T192	0	11842	0	0
T193	0	7950	0	0
T194	0	11112	0	0
T195	0	6052	0	0
T196	0	93	0	0
T198	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	49854	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	706	0	0
T185	0	4439	0	0
T190	0	2937	0	0
T191	0	3395	0	0
T201	0	117	0	0
T203	0	70	0	0
T204	0	9	0	0
T205	0	21	0	0
T206	0	80	0	0
T207	0	31	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	43911	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	903	0	0
T185	0	3758	0	0
T190	0	2177	0	0
T191	0	2988	0	0
T192	0	9964	0	0
T193	0	6725	0	0
T194	0	10498	0	0
T195	0	5671	0	0
T196	0	75	0	0
T198	0	6	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208086071	50466	0	0
T11	2297	0	0	0
T13	2416	0	0	0
T14	2401	0	0	0
T82	1947	0	0	0
T111	710	0	0	0
T133	3058	0	0	0
T147	1068	0	0	0
T148	2791	0	0	0
T149	1464	0	0	0
T184	121604	908	0	0
T185	0	4159	0	0
T190	0	2874	0	0
T191	0	3382	0	0
T192	0	11862	0	0
T193	0	7687	0	0
T194	0	12143	0	0
T195	0	6115	0	0
T196	0	91	0	0
T198	0	15	0	0