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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.99 98.27 93.63 96.79 82.66 96.87 96.58 93.15


Total test records in report: 971
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T795 /workspace/coverage/default/23.edn_disable.3128573540 Mar 10 01:37:10 PM PDT 24 Mar 10 01:37:11 PM PDT 24 45564121 ps
T796 /workspace/coverage/default/28.edn_genbits.590669004 Mar 10 01:37:25 PM PDT 24 Mar 10 01:37:27 PM PDT 24 55101966 ps
T797 /workspace/coverage/default/20.edn_smoke.3293810648 Mar 10 01:36:59 PM PDT 24 Mar 10 01:37:01 PM PDT 24 27481365 ps
T798 /workspace/coverage/default/4.edn_genbits.877400582 Mar 10 01:36:14 PM PDT 24 Mar 10 01:36:17 PM PDT 24 149869660 ps
T799 /workspace/coverage/default/113.edn_genbits.1567352747 Mar 10 01:38:35 PM PDT 24 Mar 10 01:38:37 PM PDT 24 30434725 ps
T800 /workspace/coverage/default/162.edn_genbits.4163102441 Mar 10 01:38:43 PM PDT 24 Mar 10 01:38:46 PM PDT 24 75735632 ps
T801 /workspace/coverage/default/27.edn_alert_test.1503236909 Mar 10 01:37:25 PM PDT 24 Mar 10 01:37:26 PM PDT 24 42349733 ps
T802 /workspace/coverage/default/36.edn_disable_auto_req_mode.2624848332 Mar 10 01:37:41 PM PDT 24 Mar 10 01:37:42 PM PDT 24 73966774 ps
T71 /workspace/coverage/default/99.edn_err.557607505 Mar 10 01:38:28 PM PDT 24 Mar 10 01:38:31 PM PDT 24 27860465 ps
T112 /workspace/coverage/default/91.edn_err.2549477288 Mar 10 01:38:29 PM PDT 24 Mar 10 01:38:32 PM PDT 24 20330729 ps
T803 /workspace/coverage/default/111.edn_genbits.4171706642 Mar 10 01:38:37 PM PDT 24 Mar 10 01:38:40 PM PDT 24 66687398 ps
T804 /workspace/coverage/default/34.edn_intr.833560058 Mar 10 01:37:36 PM PDT 24 Mar 10 01:37:37 PM PDT 24 28291174 ps
T805 /workspace/coverage/default/112.edn_genbits.2264205519 Mar 10 01:38:28 PM PDT 24 Mar 10 01:38:31 PM PDT 24 34920901 ps
T806 /workspace/coverage/default/85.edn_genbits.2680269588 Mar 10 01:38:21 PM PDT 24 Mar 10 01:38:22 PM PDT 24 60013850 ps
T807 /workspace/coverage/default/24.edn_disable.114752264 Mar 10 01:37:11 PM PDT 24 Mar 10 01:37:12 PM PDT 24 15305262 ps
T174 /workspace/coverage/default/22.edn_disable_auto_req_mode.4196833835 Mar 10 01:37:05 PM PDT 24 Mar 10 01:37:07 PM PDT 24 26223021 ps
T808 /workspace/coverage/default/44.edn_stress_all.2961998995 Mar 10 01:37:55 PM PDT 24 Mar 10 01:37:59 PM PDT 24 784637562 ps
T809 /workspace/coverage/default/89.edn_genbits.2901426876 Mar 10 01:38:25 PM PDT 24 Mar 10 01:38:26 PM PDT 24 243080323 ps
T810 /workspace/coverage/default/3.edn_intr.4041571152 Mar 10 01:36:07 PM PDT 24 Mar 10 01:36:08 PM PDT 24 22325881 ps
T130 /workspace/coverage/default/12.edn_intr.4007512344 Mar 10 01:36:43 PM PDT 24 Mar 10 01:36:45 PM PDT 24 21500782 ps
T811 /workspace/coverage/default/40.edn_err.1313046223 Mar 10 01:37:51 PM PDT 24 Mar 10 01:37:52 PM PDT 24 39794526 ps
T171 /workspace/coverage/default/39.edn_err.4206647081 Mar 10 01:37:46 PM PDT 24 Mar 10 01:37:47 PM PDT 24 35285105 ps
T812 /workspace/coverage/default/93.edn_genbits.2065972299 Mar 10 01:38:29 PM PDT 24 Mar 10 01:38:31 PM PDT 24 55143629 ps
T813 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3137177688 Mar 10 01:36:19 PM PDT 24 Mar 10 01:58:49 PM PDT 24 58225366040 ps
T814 /workspace/coverage/default/8.edn_stress_all.1004317488 Mar 10 01:36:28 PM PDT 24 Mar 10 01:36:31 PM PDT 24 114436654 ps
T815 /workspace/coverage/default/255.edn_genbits.1454247499 Mar 10 01:38:58 PM PDT 24 Mar 10 01:39:00 PM PDT 24 47290750 ps
T816 /workspace/coverage/default/36.edn_alert_test.3017350168 Mar 10 01:37:39 PM PDT 24 Mar 10 01:37:40 PM PDT 24 22483373 ps
T817 /workspace/coverage/default/24.edn_disable_auto_req_mode.784645159 Mar 10 01:37:10 PM PDT 24 Mar 10 01:37:11 PM PDT 24 141508865 ps
T86 /workspace/coverage/default/30.edn_err.2535611906 Mar 10 01:37:38 PM PDT 24 Mar 10 01:37:39 PM PDT 24 91006476 ps
T818 /workspace/coverage/default/239.edn_genbits.1547733056 Mar 10 01:39:03 PM PDT 24 Mar 10 01:39:06 PM PDT 24 99800807 ps
T819 /workspace/coverage/default/6.edn_alert.1909400340 Mar 10 01:36:18 PM PDT 24 Mar 10 01:36:20 PM PDT 24 26284311 ps
T820 /workspace/coverage/default/142.edn_genbits.322390535 Mar 10 01:38:39 PM PDT 24 Mar 10 01:38:41 PM PDT 24 51925281 ps
T821 /workspace/coverage/default/46.edn_alert_test.3323104850 Mar 10 01:38:00 PM PDT 24 Mar 10 01:38:01 PM PDT 24 170454094 ps
T822 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3314171844 Mar 10 01:36:38 PM PDT 24 Mar 10 01:50:30 PM PDT 24 70287605411 ps
T823 /workspace/coverage/default/44.edn_smoke.2748393537 Mar 10 01:37:55 PM PDT 24 Mar 10 01:37:56 PM PDT 24 54266076 ps
T824 /workspace/coverage/default/13.edn_err.2765340952 Mar 10 01:36:47 PM PDT 24 Mar 10 01:36:48 PM PDT 24 25905134 ps
T161 /workspace/coverage/default/12.edn_disable.543770269 Mar 10 01:36:40 PM PDT 24 Mar 10 01:36:42 PM PDT 24 32878431 ps
T825 /workspace/coverage/default/283.edn_genbits.549723581 Mar 10 01:39:05 PM PDT 24 Mar 10 01:39:06 PM PDT 24 47935402 ps
T826 /workspace/coverage/default/181.edn_genbits.3344350070 Mar 10 01:38:49 PM PDT 24 Mar 10 01:38:51 PM PDT 24 39828698 ps
T827 /workspace/coverage/default/46.edn_stress_all.942255764 Mar 10 01:37:58 PM PDT 24 Mar 10 01:38:01 PM PDT 24 77744739 ps
T828 /workspace/coverage/default/282.edn_genbits.3940328864 Mar 10 01:39:07 PM PDT 24 Mar 10 01:39:09 PM PDT 24 43433624 ps
T829 /workspace/coverage/default/101.edn_genbits.435477094 Mar 10 01:38:31 PM PDT 24 Mar 10 01:38:32 PM PDT 24 195913024 ps
T830 /workspace/coverage/default/18.edn_stress_all.1308141707 Mar 10 01:36:56 PM PDT 24 Mar 10 01:36:58 PM PDT 24 385920184 ps
T831 /workspace/coverage/default/163.edn_genbits.4173967262 Mar 10 01:38:41 PM PDT 24 Mar 10 01:38:43 PM PDT 24 44099469 ps
T832 /workspace/coverage/default/49.edn_disable_auto_req_mode.32672118 Mar 10 01:38:06 PM PDT 24 Mar 10 01:38:08 PM PDT 24 51164508 ps
T833 /workspace/coverage/default/35.edn_alert_test.691178662 Mar 10 01:37:36 PM PDT 24 Mar 10 01:37:37 PM PDT 24 76464645 ps
T834 /workspace/coverage/default/224.edn_genbits.3572588725 Mar 10 01:38:54 PM PDT 24 Mar 10 01:38:55 PM PDT 24 57918748 ps
T835 /workspace/coverage/default/79.edn_err.3568124361 Mar 10 01:38:19 PM PDT 24 Mar 10 01:38:20 PM PDT 24 31644298 ps
T836 /workspace/coverage/default/33.edn_genbits.2920869272 Mar 10 01:37:32 PM PDT 24 Mar 10 01:37:34 PM PDT 24 87350382 ps
T251 /workspace/coverage/default/0.edn_regwen.3745701097 Mar 10 01:35:49 PM PDT 24 Mar 10 01:35:50 PM PDT 24 26194485 ps
T837 /workspace/coverage/default/209.edn_genbits.2524920918 Mar 10 01:38:51 PM PDT 24 Mar 10 01:38:53 PM PDT 24 52799067 ps
T838 /workspace/coverage/default/131.edn_genbits.2405446817 Mar 10 01:38:34 PM PDT 24 Mar 10 01:38:35 PM PDT 24 82024464 ps
T290 /workspace/coverage/default/7.edn_genbits.1158818552 Mar 10 01:36:24 PM PDT 24 Mar 10 01:36:25 PM PDT 24 48151877 ps
T839 /workspace/coverage/default/5.edn_alert.3892570149 Mar 10 01:36:25 PM PDT 24 Mar 10 01:36:26 PM PDT 24 25514230 ps
T840 /workspace/coverage/default/65.edn_genbits.305835691 Mar 10 01:38:13 PM PDT 24 Mar 10 01:38:15 PM PDT 24 54979201 ps
T841 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2518015579 Mar 10 01:37:53 PM PDT 24 Mar 10 01:52:41 PM PDT 24 169665321138 ps
T217 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2704718320 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 46867448 ps
T197 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2047881909 Mar 10 01:07:26 PM PDT 24 Mar 10 01:07:27 PM PDT 24 40245138 ps
T842 /workspace/coverage/cover_reg_top/43.edn_intr_test.1874331605 Mar 10 01:07:55 PM PDT 24 Mar 10 01:07:57 PM PDT 24 72209556 ps
T843 /workspace/coverage/cover_reg_top/25.edn_intr_test.3706459390 Mar 10 01:07:50 PM PDT 24 Mar 10 01:07:51 PM PDT 24 11960257 ps
T844 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3319215558 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:26 PM PDT 24 47790375 ps
T845 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2551379534 Mar 10 01:07:49 PM PDT 24 Mar 10 01:07:51 PM PDT 24 50728223 ps
T231 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.112008491 Mar 10 01:07:49 PM PDT 24 Mar 10 01:07:51 PM PDT 24 54280943 ps
T846 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3539447152 Mar 10 01:07:22 PM PDT 24 Mar 10 01:07:24 PM PDT 24 27721868 ps
T232 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1814585327 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:07 PM PDT 24 99927833 ps
T847 /workspace/coverage/cover_reg_top/38.edn_intr_test.91126583 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 75859838 ps
T229 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3865470019 Mar 10 01:07:39 PM PDT 24 Mar 10 01:07:41 PM PDT 24 29023406 ps
T848 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1290702742 Mar 10 01:07:48 PM PDT 24 Mar 10 01:07:49 PM PDT 24 19711096 ps
T230 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1133317278 Mar 10 01:07:50 PM PDT 24 Mar 10 01:07:51 PM PDT 24 53319063 ps
T198 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2182143589 Mar 10 01:07:05 PM PDT 24 Mar 10 01:07:07 PM PDT 24 170105671 ps
T849 /workspace/coverage/cover_reg_top/14.edn_intr_test.376617347 Mar 10 01:07:41 PM PDT 24 Mar 10 01:07:42 PM PDT 24 161085845 ps
T850 /workspace/coverage/cover_reg_top/8.edn_tl_errors.654134893 Mar 10 01:07:25 PM PDT 24 Mar 10 01:07:29 PM PDT 24 492666445 ps
T851 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3097343003 Mar 10 01:07:35 PM PDT 24 Mar 10 01:07:38 PM PDT 24 906352669 ps
T199 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2476448293 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:42 PM PDT 24 314727386 ps
T852 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2190747244 Mar 10 01:07:38 PM PDT 24 Mar 10 01:07:39 PM PDT 24 98351653 ps
T218 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1235405635 Mar 10 01:07:10 PM PDT 24 Mar 10 01:07:11 PM PDT 24 54961659 ps
T853 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1481542659 Mar 10 01:07:42 PM PDT 24 Mar 10 01:07:43 PM PDT 24 22247596 ps
T854 /workspace/coverage/cover_reg_top/11.edn_intr_test.2927205559 Mar 10 01:07:29 PM PDT 24 Mar 10 01:07:30 PM PDT 24 16217929 ps
T855 /workspace/coverage/cover_reg_top/41.edn_intr_test.3509484560 Mar 10 01:07:52 PM PDT 24 Mar 10 01:07:53 PM PDT 24 20862361 ps
T856 /workspace/coverage/cover_reg_top/35.edn_intr_test.975477742 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 50083616 ps
T200 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2356543044 Mar 10 01:07:20 PM PDT 24 Mar 10 01:07:21 PM PDT 24 41837150 ps
T857 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1797814050 Mar 10 01:07:11 PM PDT 24 Mar 10 01:07:15 PM PDT 24 348531857 ps
T858 /workspace/coverage/cover_reg_top/42.edn_intr_test.1581281605 Mar 10 01:07:58 PM PDT 24 Mar 10 01:07:59 PM PDT 24 189580055 ps
T859 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2987765605 Mar 10 01:07:48 PM PDT 24 Mar 10 01:07:50 PM PDT 24 175802578 ps
T860 /workspace/coverage/cover_reg_top/37.edn_intr_test.1238455664 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 22461375 ps
T861 /workspace/coverage/cover_reg_top/49.edn_intr_test.2440051153 Mar 10 01:08:00 PM PDT 24 Mar 10 01:08:01 PM PDT 24 23022399 ps
T862 /workspace/coverage/cover_reg_top/21.edn_intr_test.4000078248 Mar 10 01:07:53 PM PDT 24 Mar 10 01:07:54 PM PDT 24 18984314 ps
T201 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.299429658 Mar 10 01:07:38 PM PDT 24 Mar 10 01:07:39 PM PDT 24 74886161 ps
T863 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.239838981 Mar 10 01:07:02 PM PDT 24 Mar 10 01:07:08 PM PDT 24 182442619 ps
T864 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3141892492 Mar 10 01:07:10 PM PDT 24 Mar 10 01:07:11 PM PDT 24 188391614 ps
T865 /workspace/coverage/cover_reg_top/34.edn_intr_test.66325906 Mar 10 01:07:53 PM PDT 24 Mar 10 01:07:55 PM PDT 24 22974869 ps
T202 /workspace/coverage/cover_reg_top/9.edn_csr_rw.145298619 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:25 PM PDT 24 14219546 ps
T203 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3139608071 Mar 10 01:07:20 PM PDT 24 Mar 10 01:07:22 PM PDT 24 51899239 ps
T866 /workspace/coverage/cover_reg_top/4.edn_intr_test.3533687165 Mar 10 01:07:11 PM PDT 24 Mar 10 01:07:12 PM PDT 24 12872044 ps
T204 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1652719715 Mar 10 01:07:49 PM PDT 24 Mar 10 01:07:50 PM PDT 24 10968887 ps
T867 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.787227940 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:22 PM PDT 24 58994317 ps
T219 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3171299050 Mar 10 01:07:22 PM PDT 24 Mar 10 01:07:23 PM PDT 24 56766416 ps
T205 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1003940491 Mar 10 01:07:48 PM PDT 24 Mar 10 01:07:50 PM PDT 24 224302035 ps
T233 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2676281524 Mar 10 01:07:24 PM PDT 24 Mar 10 01:07:26 PM PDT 24 195023877 ps
T868 /workspace/coverage/cover_reg_top/33.edn_intr_test.305493397 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 14159003 ps
T869 /workspace/coverage/cover_reg_top/30.edn_intr_test.2638586774 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 20341969 ps
T870 /workspace/coverage/cover_reg_top/8.edn_csr_rw.935233669 Mar 10 01:07:26 PM PDT 24 Mar 10 01:07:27 PM PDT 24 22793366 ps
T206 /workspace/coverage/cover_reg_top/11.edn_csr_rw.655762768 Mar 10 01:07:34 PM PDT 24 Mar 10 01:07:35 PM PDT 24 30652994 ps
T871 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3760579157 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:20 PM PDT 24 17287323 ps
T872 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.12886607 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:25 PM PDT 24 72041543 ps
T873 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2267995197 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:19 PM PDT 24 32000797 ps
T874 /workspace/coverage/cover_reg_top/0.edn_tl_errors.889006432 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:03 PM PDT 24 80892455 ps
T244 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3203461310 Mar 10 01:07:13 PM PDT 24 Mar 10 01:07:15 PM PDT 24 314977452 ps
T875 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1873409089 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:42 PM PDT 24 52013329 ps
T876 /workspace/coverage/cover_reg_top/24.edn_intr_test.4118532019 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 96328441 ps
T239 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2235400679 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:48 PM PDT 24 148634308 ps
T877 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2093455812 Mar 10 01:07:44 PM PDT 24 Mar 10 01:07:46 PM PDT 24 32555628 ps
T878 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2457198692 Mar 10 01:07:21 PM PDT 24 Mar 10 01:07:22 PM PDT 24 16715473 ps
T879 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1325499032 Mar 10 01:07:00 PM PDT 24 Mar 10 01:07:01 PM PDT 24 26046450 ps
T240 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3030809423 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:08 PM PDT 24 96502941 ps
T880 /workspace/coverage/cover_reg_top/23.edn_intr_test.2563978248 Mar 10 01:07:52 PM PDT 24 Mar 10 01:07:53 PM PDT 24 21349941 ps
T881 /workspace/coverage/cover_reg_top/46.edn_intr_test.2069409558 Mar 10 01:08:06 PM PDT 24 Mar 10 01:08:07 PM PDT 24 27156606 ps
T882 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4117855446 Mar 10 01:07:15 PM PDT 24 Mar 10 01:07:17 PM PDT 24 72974425 ps
T883 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4098167352 Mar 10 01:07:38 PM PDT 24 Mar 10 01:07:40 PM PDT 24 257613342 ps
T884 /workspace/coverage/cover_reg_top/15.edn_intr_test.615744988 Mar 10 01:07:41 PM PDT 24 Mar 10 01:07:42 PM PDT 24 15447687 ps
T885 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1392370248 Mar 10 01:07:27 PM PDT 24 Mar 10 01:07:28 PM PDT 24 42968044 ps
T207 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1018779974 Mar 10 01:07:03 PM PDT 24 Mar 10 01:07:04 PM PDT 24 18185508 ps
T886 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2448676110 Mar 10 01:07:39 PM PDT 24 Mar 10 01:07:42 PM PDT 24 618980935 ps
T887 /workspace/coverage/cover_reg_top/6.edn_intr_test.1557877336 Mar 10 01:07:19 PM PDT 24 Mar 10 01:07:20 PM PDT 24 13873280 ps
T888 /workspace/coverage/cover_reg_top/28.edn_intr_test.2707408272 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 31451316 ps
T889 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3208736490 Mar 10 01:07:16 PM PDT 24 Mar 10 01:07:22 PM PDT 24 1891492379 ps
T890 /workspace/coverage/cover_reg_top/0.edn_intr_test.1601863712 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:02 PM PDT 24 74724492 ps
T891 /workspace/coverage/cover_reg_top/45.edn_intr_test.1223940073 Mar 10 01:07:57 PM PDT 24 Mar 10 01:07:58 PM PDT 24 45252175 ps
T892 /workspace/coverage/cover_reg_top/17.edn_csr_rw.81078862 Mar 10 01:07:47 PM PDT 24 Mar 10 01:07:48 PM PDT 24 20885578 ps
T893 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2382490220 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:08 PM PDT 24 57378882 ps
T894 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2771746798 Mar 10 01:07:21 PM PDT 24 Mar 10 01:07:23 PM PDT 24 860750989 ps
T895 /workspace/coverage/cover_reg_top/48.edn_intr_test.2164181440 Mar 10 01:07:57 PM PDT 24 Mar 10 01:07:58 PM PDT 24 111937338 ps
T896 /workspace/coverage/cover_reg_top/5.edn_intr_test.1453273587 Mar 10 01:07:16 PM PDT 24 Mar 10 01:07:17 PM PDT 24 19781008 ps
T897 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4250871258 Mar 10 01:07:16 PM PDT 24 Mar 10 01:07:18 PM PDT 24 43143193 ps
T898 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2825676318 Mar 10 01:07:06 PM PDT 24 Mar 10 01:07:07 PM PDT 24 22758858 ps
T241 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.160910649 Mar 10 01:07:11 PM PDT 24 Mar 10 01:07:14 PM PDT 24 138625413 ps
T899 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1290006857 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:03 PM PDT 24 157545429 ps
T900 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2831479950 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:24 PM PDT 24 41693496 ps
T245 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.424201018 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:43 PM PDT 24 253441846 ps
T208 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3332477678 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:06 PM PDT 24 52266740 ps
T901 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2719845760 Mar 10 01:07:33 PM PDT 24 Mar 10 01:07:35 PM PDT 24 35116564 ps
T902 /workspace/coverage/cover_reg_top/12.edn_intr_test.181082099 Mar 10 01:07:34 PM PDT 24 Mar 10 01:07:35 PM PDT 24 37645038 ps
T903 /workspace/coverage/cover_reg_top/32.edn_intr_test.1104720882 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 23000547 ps
T904 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3674249543 Mar 10 01:07:12 PM PDT 24 Mar 10 01:07:15 PM PDT 24 77140009 ps
T905 /workspace/coverage/cover_reg_top/1.edn_csr_rw.837262651 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:03 PM PDT 24 40153599 ps
T906 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1434372372 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:22 PM PDT 24 145425905 ps
T209 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3846292046 Mar 10 01:07:43 PM PDT 24 Mar 10 01:07:44 PM PDT 24 13215251 ps
T211 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.732216277 Mar 10 01:06:59 PM PDT 24 Mar 10 01:07:06 PM PDT 24 253861826 ps
T907 /workspace/coverage/cover_reg_top/26.edn_intr_test.837291230 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 14904257 ps
T908 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3676300293 Mar 10 01:07:29 PM PDT 24 Mar 10 01:07:32 PM PDT 24 76180648 ps
T909 /workspace/coverage/cover_reg_top/8.edn_intr_test.2476209942 Mar 10 01:07:27 PM PDT 24 Mar 10 01:07:28 PM PDT 24 153911556 ps
T910 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1927934647 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:25 PM PDT 24 53990269 ps
T911 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.581211743 Mar 10 01:07:39 PM PDT 24 Mar 10 01:07:41 PM PDT 24 113758955 ps
T912 /workspace/coverage/cover_reg_top/22.edn_intr_test.2269360949 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 26425109 ps
T913 /workspace/coverage/cover_reg_top/31.edn_intr_test.2260076879 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 11825252 ps
T914 /workspace/coverage/cover_reg_top/17.edn_tl_errors.87361141 Mar 10 01:07:47 PM PDT 24 Mar 10 01:07:49 PM PDT 24 577238657 ps
T915 /workspace/coverage/cover_reg_top/29.edn_intr_test.2584620087 Mar 10 01:07:52 PM PDT 24 Mar 10 01:07:53 PM PDT 24 34236519 ps
T916 /workspace/coverage/cover_reg_top/2.edn_csr_rw.718392349 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:05 PM PDT 24 81796775 ps
T917 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.800917896 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:20 PM PDT 24 27668751 ps
T918 /workspace/coverage/cover_reg_top/3.edn_intr_test.523120431 Mar 10 01:07:11 PM PDT 24 Mar 10 01:07:12 PM PDT 24 49655228 ps
T919 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2928414452 Mar 10 01:07:02 PM PDT 24 Mar 10 01:07:04 PM PDT 24 118095213 ps
T920 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.499998156 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:47 PM PDT 24 40416170 ps
T921 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3719876277 Mar 10 01:07:06 PM PDT 24 Mar 10 01:07:07 PM PDT 24 119562633 ps
T242 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2453985473 Mar 10 01:07:19 PM PDT 24 Mar 10 01:07:21 PM PDT 24 91006121 ps
T922 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2813222324 Mar 10 01:07:21 PM PDT 24 Mar 10 01:07:23 PM PDT 24 30631935 ps
T923 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1119779718 Mar 10 01:07:47 PM PDT 24 Mar 10 01:07:48 PM PDT 24 17461152 ps
T924 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2571413330 Mar 10 01:07:39 PM PDT 24 Mar 10 01:07:40 PM PDT 24 51309715 ps
T210 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1911190667 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:20 PM PDT 24 14514983 ps
T925 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4186274113 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:04 PM PDT 24 183376919 ps
T926 /workspace/coverage/cover_reg_top/36.edn_intr_test.219571260 Mar 10 01:07:58 PM PDT 24 Mar 10 01:07:59 PM PDT 24 43486643 ps
T927 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.553516953 Mar 10 01:07:29 PM PDT 24 Mar 10 01:07:32 PM PDT 24 324666952 ps
T928 /workspace/coverage/cover_reg_top/2.edn_intr_test.2938766048 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:05 PM PDT 24 49736171 ps
T929 /workspace/coverage/cover_reg_top/40.edn_intr_test.3885426156 Mar 10 01:07:58 PM PDT 24 Mar 10 01:07:59 PM PDT 24 14769420 ps
T930 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2908014551 Mar 10 01:07:12 PM PDT 24 Mar 10 01:07:15 PM PDT 24 29956171 ps
T212 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3244851594 Mar 10 01:07:17 PM PDT 24 Mar 10 01:07:19 PM PDT 24 53811789 ps
T931 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2654179885 Mar 10 01:07:39 PM PDT 24 Mar 10 01:07:42 PM PDT 24 326334890 ps
T932 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2456405588 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:50 PM PDT 24 123624559 ps
T933 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3253677652 Mar 10 01:07:27 PM PDT 24 Mar 10 01:07:28 PM PDT 24 27343356 ps
T934 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1523319585 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:48 PM PDT 24 34627954 ps
T935 /workspace/coverage/cover_reg_top/7.edn_intr_test.3217242111 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:19 PM PDT 24 43257390 ps
T936 /workspace/coverage/cover_reg_top/17.edn_intr_test.3934155577 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:48 PM PDT 24 19975153 ps
T937 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.757185656 Mar 10 01:07:24 PM PDT 24 Mar 10 01:07:26 PM PDT 24 146746833 ps
T938 /workspace/coverage/cover_reg_top/2.edn_tl_errors.75595687 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:06 PM PDT 24 63031919 ps
T213 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4078470610 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:47 PM PDT 24 19296816 ps
T939 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2540144157 Mar 10 01:07:01 PM PDT 24 Mar 10 01:07:03 PM PDT 24 56137383 ps
T940 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2635625151 Mar 10 01:06:58 PM PDT 24 Mar 10 01:06:59 PM PDT 24 41134437 ps
T941 /workspace/coverage/cover_reg_top/9.edn_intr_test.2709183387 Mar 10 01:07:25 PM PDT 24 Mar 10 01:07:26 PM PDT 24 35851310 ps
T942 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3334694776 Mar 10 01:07:43 PM PDT 24 Mar 10 01:07:44 PM PDT 24 20909245 ps
T943 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1706839463 Mar 10 01:07:13 PM PDT 24 Mar 10 01:07:14 PM PDT 24 49504674 ps
T944 /workspace/coverage/cover_reg_top/13.edn_intr_test.4031232793 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:41 PM PDT 24 15680519 ps
T945 /workspace/coverage/cover_reg_top/16.edn_intr_test.1012891354 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:41 PM PDT 24 25773494 ps
T946 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3467162315 Mar 10 01:07:23 PM PDT 24 Mar 10 01:07:28 PM PDT 24 560154643 ps
T947 /workspace/coverage/cover_reg_top/10.edn_csr_rw.308670387 Mar 10 01:07:27 PM PDT 24 Mar 10 01:07:28 PM PDT 24 13584564 ps
T948 /workspace/coverage/cover_reg_top/10.edn_intr_test.2913398662 Mar 10 01:07:27 PM PDT 24 Mar 10 01:07:28 PM PDT 24 12646421 ps
T949 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.177973307 Mar 10 01:07:22 PM PDT 24 Mar 10 01:07:23 PM PDT 24 59107815 ps
T950 /workspace/coverage/cover_reg_top/1.edn_intr_test.1497107 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:05 PM PDT 24 16087331 ps
T951 /workspace/coverage/cover_reg_top/27.edn_intr_test.1112008317 Mar 10 01:07:54 PM PDT 24 Mar 10 01:07:55 PM PDT 24 13220704 ps
T952 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3720112163 Mar 10 01:07:28 PM PDT 24 Mar 10 01:07:30 PM PDT 24 320915178 ps
T953 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1407356946 Mar 10 01:07:46 PM PDT 24 Mar 10 01:07:48 PM PDT 24 62204100 ps
T214 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1089970235 Mar 10 01:07:09 PM PDT 24 Mar 10 01:07:10 PM PDT 24 48135615 ps
T243 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.625953076 Mar 10 01:07:45 PM PDT 24 Mar 10 01:07:48 PM PDT 24 75986795 ps
T954 /workspace/coverage/cover_reg_top/44.edn_intr_test.4014944023 Mar 10 01:07:56 PM PDT 24 Mar 10 01:07:57 PM PDT 24 20103407 ps
T215 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.616431735 Mar 10 01:07:02 PM PDT 24 Mar 10 01:07:04 PM PDT 24 35509588 ps
T955 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.528555842 Mar 10 01:07:18 PM PDT 24 Mar 10 01:07:21 PM PDT 24 206460257 ps
T956 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.263960609 Mar 10 01:07:40 PM PDT 24 Mar 10 01:07:41 PM PDT 24 26953117 ps
T957 /workspace/coverage/cover_reg_top/15.edn_tl_errors.976466701 Mar 10 01:07:42 PM PDT 24 Mar 10 01:07:46 PM PDT 24 241690123 ps
T958 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3785464833 Mar 10 01:07:49 PM PDT 24 Mar 10 01:07:52 PM PDT 24 324797662 ps
T959 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.636661486 Mar 10 01:07:15 PM PDT 24 Mar 10 01:07:16 PM PDT 24 49661846 ps
T216 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3621366291 Mar 10 01:07:00 PM PDT 24 Mar 10 01:07:02 PM PDT 24 15212166 ps
T960 /workspace/coverage/cover_reg_top/18.edn_intr_test.2773866058 Mar 10 01:07:48 PM PDT 24 Mar 10 01:07:49 PM PDT 24 25606739 ps
T961 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1773860107 Mar 10 01:07:50 PM PDT 24 Mar 10 01:07:52 PM PDT 24 74409450 ps
T962 /workspace/coverage/cover_reg_top/39.edn_intr_test.1522622385 Mar 10 01:07:53 PM PDT 24 Mar 10 01:07:55 PM PDT 24 26194770 ps
T963 /workspace/coverage/cover_reg_top/19.edn_intr_test.717579885 Mar 10 01:07:51 PM PDT 24 Mar 10 01:07:52 PM PDT 24 15923627 ps
T964 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.370149947 Mar 10 01:07:38 PM PDT 24 Mar 10 01:07:39 PM PDT 24 108225349 ps
T965 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2988062119 Mar 10 01:07:28 PM PDT 24 Mar 10 01:07:29 PM PDT 24 32381689 ps
T966 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2323493170 Mar 10 01:07:41 PM PDT 24 Mar 10 01:07:43 PM PDT 24 25597638 ps
T967 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.226159811 Mar 10 01:07:30 PM PDT 24 Mar 10 01:07:31 PM PDT 24 118883773 ps
T968 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2439667482 Mar 10 01:07:49 PM PDT 24 Mar 10 01:07:51 PM PDT 24 52153840 ps
T969 /workspace/coverage/cover_reg_top/20.edn_intr_test.2173879458 Mar 10 01:07:52 PM PDT 24 Mar 10 01:07:53 PM PDT 24 15961952 ps
T970 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2215275439 Mar 10 01:07:03 PM PDT 24 Mar 10 01:07:04 PM PDT 24 213149380 ps
T971 /workspace/coverage/cover_reg_top/47.edn_intr_test.451696790 Mar 10 01:07:59 PM PDT 24 Mar 10 01:08:00 PM PDT 24 10724339 ps

Test location /workspace/coverage/default/150.edn_genbits.1067298388
Short name T10
Test name
Test status
Simulation time 167985732 ps
CPU time 2.97 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:45 PM PDT 24
Peak memory 218252 kb
Host smart-aec39d49-718b-4d25-aafe-4dcfcc3a1d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067298388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1067298388
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.13778493
Short name T25
Test name
Test status
Simulation time 110506578987 ps
CPU time 274.74 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 222812 kb
Host smart-61a1817e-d120-4fbc-8f51-470ec5bea4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778493 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.13778493
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_genbits.2018437220
Short name T35
Test name
Test status
Simulation time 65432485 ps
CPU time 2.72 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:03 PM PDT 24
Peak memory 216956 kb
Host smart-3f3375a3-3dff-4b31-9fcb-9022784a1518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018437220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2018437220
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.200228990
Short name T19
Test name
Test status
Simulation time 47812304 ps
CPU time 1.17 seconds
Started Mar 10 01:35:56 PM PDT 24
Finished Mar 10 01:35:57 PM PDT 24
Peak memory 214788 kb
Host smart-9f05ad9b-8e22-4704-a59d-f2243d5154a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200228990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.200228990
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2346979658
Short name T16
Test name
Test status
Simulation time 163452154 ps
CPU time 3.48 seconds
Started Mar 10 01:36:15 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 240156 kb
Host smart-584481b6-5fa9-4e5f-8d8e-84033fabc7aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346979658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2346979658
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/19.edn_stress_all.3140661234
Short name T144
Test name
Test status
Simulation time 212304210 ps
CPU time 4.58 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:10 PM PDT 24
Peak memory 215596 kb
Host smart-7aa20b71-40fd-4c2c-9366-483aa2897b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140661234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3140661234
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_err.2163096557
Short name T9
Test name
Test status
Simulation time 25424506 ps
CPU time 1.37 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:58 PM PDT 24
Peak memory 228976 kb
Host smart-41007b58-ace8-4880-b5ba-8bad952e6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163096557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2163096557
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1552736843
Short name T21
Test name
Test status
Simulation time 334429124 ps
CPU time 5.71 seconds
Started Mar 10 01:36:00 PM PDT 24
Finished Mar 10 01:36:06 PM PDT 24
Peak memory 237272 kb
Host smart-8a95267e-5089-41d9-bdf5-76be6ded8558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552736843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1552736843
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_alert.2372981490
Short name T260
Test name
Test status
Simulation time 25277299 ps
CPU time 1.32 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:06 PM PDT 24
Peak memory 214824 kb
Host smart-cfe66668-6f94-48e4-9b84-8ccea9e86ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372981490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2372981490
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1872348263
Short name T30
Test name
Test status
Simulation time 37207530 ps
CPU time 1.06 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 215576 kb
Host smart-4befd262-50c3-4a1d-bab0-bf8d48c81813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872348263 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1872348263
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_regwen.2335016703
Short name T120
Test name
Test status
Simulation time 32939087 ps
CPU time 0.9 seconds
Started Mar 10 01:35:55 PM PDT 24
Finished Mar 10 01:35:56 PM PDT 24
Peak memory 206212 kb
Host smart-37f48f36-3b22-4ee2-9288-ff83c0235a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335016703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2335016703
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_intr.1058965964
Short name T127
Test name
Test status
Simulation time 64591377 ps
CPU time 0.86 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 214632 kb
Host smart-cea6b20f-cec3-4c79-9939-495aa5998aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058965964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1058965964
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/39.edn_disable.75952334
Short name T60
Test name
Test status
Simulation time 33220171 ps
CPU time 0.85 seconds
Started Mar 10 01:37:47 PM PDT 24
Finished Mar 10 01:37:48 PM PDT 24
Peak memory 215032 kb
Host smart-4a4521b8-0dc5-4b21-be4e-36d94022df0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75952334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.75952334
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/184.edn_genbits.3608001126
Short name T29
Test name
Test status
Simulation time 291928680 ps
CPU time 4.18 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:52 PM PDT 24
Peak memory 218700 kb
Host smart-a425e2ab-95cb-4618-8d02-c7222bce6fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608001126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3608001126
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.4107087596
Short name T136
Test name
Test status
Simulation time 72571500270 ps
CPU time 855.38 seconds
Started Mar 10 01:37:41 PM PDT 24
Finished Mar 10 01:51:57 PM PDT 24
Peak memory 219284 kb
Host smart-08b5bca5-e8b2-4f14-8ff3-63610a984066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107087596 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.4107087596
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1652719715
Short name T204
Test name
Test status
Simulation time 10968887 ps
CPU time 0.85 seconds
Started Mar 10 01:07:49 PM PDT 24
Finished Mar 10 01:07:50 PM PDT 24
Peak memory 206284 kb
Host smart-92381005-90d0-4ced-a0ae-e09065779213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652719715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1652719715
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.424201018
Short name T245
Test name
Test status
Simulation time 253441846 ps
CPU time 2.16 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:43 PM PDT 24
Peak memory 206344 kb
Host smart-9c534c4e-e10e-40d4-b3d1-962593283700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424201018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.424201018
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/19.edn_alert.2793647470
Short name T101
Test name
Test status
Simulation time 46948352 ps
CPU time 1.15 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 214756 kb
Host smart-21710ebd-a4f3-46e3-a2e3-72d87bb57496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793647470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2793647470
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert.551982498
Short name T490
Test name
Test status
Simulation time 76581769 ps
CPU time 1.16 seconds
Started Mar 10 01:37:30 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 214768 kb
Host smart-1e3f5315-2d50-4715-921c-af61cc387d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551982498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.551982498
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.1601727906
Short name T92
Test name
Test status
Simulation time 18378203 ps
CPU time 0.83 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:06 PM PDT 24
Peak memory 214908 kb
Host smart-2c34bcb9-9e7c-4991-a5bd-e51628f90ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601727906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1601727906
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable.2151184856
Short name T172
Test name
Test status
Simulation time 11706942 ps
CPU time 0.94 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 214972 kb
Host smart-8f2375f3-e374-467a-8d47-da42a92c1aee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151184856 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2151184856
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.2912549796
Short name T105
Test name
Test status
Simulation time 15542737 ps
CPU time 0.92 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 214956 kb
Host smart-0f2175a7-9f76-464d-9a03-6155134e6805
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912549796 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2912549796
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1754510942
Short name T67
Test name
Test status
Simulation time 44687077 ps
CPU time 1.43 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:22 PM PDT 24
Peak memory 215612 kb
Host smart-040cfa8f-eeaf-4084-a5ef-b68205abe11f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754510942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1754510942
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_intr.3484562216
Short name T131
Test name
Test status
Simulation time 36708423 ps
CPU time 0.87 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:51 PM PDT 24
Peak memory 214676 kb
Host smart-9e8bad17-5abc-4b48-a41a-7a14b8fb35e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484562216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3484562216
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/30.edn_disable.3635409430
Short name T32
Test name
Test status
Simulation time 10445605 ps
CPU time 0.89 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:26 PM PDT 24
Peak memory 214892 kb
Host smart-6c32cbea-5791-4db8-a440-1c8e3e807202
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635409430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3635409430
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/244.edn_genbits.3257957752
Short name T36
Test name
Test status
Simulation time 55245701 ps
CPU time 1.9 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:05 PM PDT 24
Peak memory 218376 kb
Host smart-5d29cfd6-d890-4c36-88d9-325627ceb22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257957752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3257957752
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1311466368
Short name T51
Test name
Test status
Simulation time 85582036 ps
CPU time 1.12 seconds
Started Mar 10 01:38:06 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 214736 kb
Host smart-fa265110-7fb3-45a9-ae6f-65b843fc5db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311466368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1311466368
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_alert.7725970
Short name T253
Test name
Test status
Simulation time 43492256 ps
CPU time 1.18 seconds
Started Mar 10 01:36:48 PM PDT 24
Finished Mar 10 01:36:49 PM PDT 24
Peak memory 214792 kb
Host smart-77eac22b-0f6b-49d2-869b-2961e90ddb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7725970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.7725970
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1324165792
Short name T266
Test name
Test status
Simulation time 53207274 ps
CPU time 1.47 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 215716 kb
Host smart-d28b85d9-b22f-474c-87ad-74e097ec735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324165792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1324165792
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2215043999
Short name T439
Test name
Test status
Simulation time 44687082 ps
CPU time 1.51 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:44 PM PDT 24
Peak memory 216788 kb
Host smart-57915db2-b5a0-48bd-a972-52b47427797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215043999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2215043999
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.1692117452
Short name T88
Test name
Test status
Simulation time 12642515 ps
CPU time 0.91 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:35 PM PDT 24
Peak memory 214668 kb
Host smart-750f55e2-69bb-4aad-b999-e9aa56311e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692117452 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1692117452
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable.625053448
Short name T540
Test name
Test status
Simulation time 10544243 ps
CPU time 0.87 seconds
Started Mar 10 01:36:13 PM PDT 24
Finished Mar 10 01:36:14 PM PDT 24
Peak memory 214892 kb
Host smart-6d38b808-51af-4a58-aaf0-a0033186c19b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625053448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.625053448
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.4013398037
Short name T166
Test name
Test status
Simulation time 41134196 ps
CPU time 0.91 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 214860 kb
Host smart-631c7905-8a04-4372-b6e6-abbd3e7920bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013398037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4013398037
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2958387795
Short name T82
Test name
Test status
Simulation time 78290597 ps
CPU time 1.03 seconds
Started Mar 10 01:37:07 PM PDT 24
Finished Mar 10 01:37:09 PM PDT 24
Peak memory 215384 kb
Host smart-a244182f-17fe-41cb-8f4d-de2b8ad2c216
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958387795 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2958387795
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_disable.4028859097
Short name T175
Test name
Test status
Simulation time 21614796 ps
CPU time 0.88 seconds
Started Mar 10 01:37:30 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 215040 kb
Host smart-551bf4cc-c429-427f-8c08-2e41574c129c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028859097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4028859097
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.3021802352
Short name T163
Test name
Test status
Simulation time 130755077 ps
CPU time 0.9 seconds
Started Mar 10 01:37:32 PM PDT 24
Finished Mar 10 01:37:33 PM PDT 24
Peak memory 214856 kb
Host smart-1974ac3d-5fef-4612-8b26-c8a22af993a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021802352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3021802352
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.1586575078
Short name T115
Test name
Test status
Simulation time 26086696 ps
CPU time 0.81 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:56 PM PDT 24
Peak memory 214916 kb
Host smart-146ae7f7-ec69-4fed-9ff6-5156410481ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586575078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1586575078
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable.3705067188
Short name T160
Test name
Test status
Simulation time 46105701 ps
CPU time 0.83 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:24 PM PDT 24
Peak memory 214908 kb
Host smart-5a54325d-0f7c-4ebc-9894-98b2d6d3631a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705067188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3705067188
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/6.edn_regwen.2185858250
Short name T256
Test name
Test status
Simulation time 106965764 ps
CPU time 0.93 seconds
Started Mar 10 01:36:15 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 206196 kb
Host smart-fad31e10-ad13-4da3-9299-ca4cd627e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185858250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2185858250
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_alert_test.2495456594
Short name T299
Test name
Test status
Simulation time 56920274 ps
CPU time 0.97 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 205748 kb
Host smart-8c0f3a46-6245-4704-bc84-1e8eb2296458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495456594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2495456594
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/142.edn_genbits.322390535
Short name T820
Test name
Test status
Simulation time 51925281 ps
CPU time 1.26 seconds
Started Mar 10 01:38:39 PM PDT 24
Finished Mar 10 01:38:41 PM PDT 24
Peak memory 218192 kb
Host smart-f52efebc-d2c8-46d3-a83c-39b384c6fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322390535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.322390535
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2547994615
Short name T319
Test name
Test status
Simulation time 38032623 ps
CPU time 1.55 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:45 PM PDT 24
Peak memory 216936 kb
Host smart-e01565f1-e88b-4683-88f4-a46ce7673f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547994615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2547994615
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4176072297
Short name T262
Test name
Test status
Simulation time 76525137 ps
CPU time 1.1 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 215528 kb
Host smart-12803211-48a3-4865-9512-d26cabb5b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176072297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4176072297
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3370772848
Short name T190
Test name
Test status
Simulation time 34909540613 ps
CPU time 544.36 seconds
Started Mar 10 01:36:45 PM PDT 24
Finished Mar 10 01:45:50 PM PDT 24
Peak memory 222780 kb
Host smart-910252b8-4c06-4a54-aa76-b5f8c66979ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370772848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3370772848
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_intr.4007512344
Short name T130
Test name
Test status
Simulation time 21500782 ps
CPU time 1.07 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:36:45 PM PDT 24
Peak memory 214792 kb
Host smart-fac77d76-9811-43b7-9d71-2e653a4c3bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007512344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4007512344
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/11.edn_genbits.3977666662
Short name T13
Test name
Test status
Simulation time 38097247 ps
CPU time 1.49 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:35 PM PDT 24
Peak memory 218316 kb
Host smart-e1d5b2b7-37e0-4855-b73d-3d93419afc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977666662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3977666662
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1803657552
Short name T657
Test name
Test status
Simulation time 38563626 ps
CPU time 1.65 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 218548 kb
Host smart-85d94c49-9291-4e5d-a697-3f41366f970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803657552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1803657552
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2476448293
Short name T199
Test name
Test status
Simulation time 314727386 ps
CPU time 1.19 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 206328 kb
Host smart-08f68543-e593-4d93-9bd7-c57256286a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476448293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2476448293
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.625953076
Short name T243
Test name
Test status
Simulation time 75986795 ps
CPU time 2.02 seconds
Started Mar 10 01:07:45 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 206424 kb
Host smart-2cc288c7-0b57-4624-a99f-5ca1af65287a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625953076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.625953076
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/101.edn_genbits.435477094
Short name T829
Test name
Test status
Simulation time 195913024 ps
CPU time 1.06 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:32 PM PDT 24
Peak memory 215544 kb
Host smart-f3bca89b-3537-4434-8637-ed9683df2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435477094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.435477094
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.675107823
Short name T228
Test name
Test status
Simulation time 44622083 ps
CPU time 1.22 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:41 PM PDT 24
Peak memory 214768 kb
Host smart-b8a45c75-f48e-4ccc-a93d-e033a8e973e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675107823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.675107823
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1765843008
Short name T289
Test name
Test status
Simulation time 83841204 ps
CPU time 1.26 seconds
Started Mar 10 01:38:36 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 217148 kb
Host smart-0c2cd21e-3d01-4994-aad2-3ac1ccf0e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765843008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1765843008
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2682259300
Short name T272
Test name
Test status
Simulation time 46021734 ps
CPU time 1.68 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 217032 kb
Host smart-6adeee52-9bec-4303-a80b-0a51493d1b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682259300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2682259300
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_genbits.11319078
Short name T268
Test name
Test status
Simulation time 105239447 ps
CPU time 1.38 seconds
Started Mar 10 01:36:55 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 217112 kb
Host smart-1a5fc8b1-08ab-4880-95ab-f13f3ff83b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11319078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.11319078
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2573095004
Short name T639
Test name
Test status
Simulation time 52654762442 ps
CPU time 1316.14 seconds
Started Mar 10 01:36:59 PM PDT 24
Finished Mar 10 01:58:56 PM PDT 24
Peak memory 221904 kb
Host smart-a28ac045-3db3-4e48-a4f1-5bacc34c4775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573095004 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2573095004
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_regwen.3277787976
Short name T119
Test name
Test status
Simulation time 75050275 ps
CPU time 0.88 seconds
Started Mar 10 01:36:01 PM PDT 24
Finished Mar 10 01:36:02 PM PDT 24
Peak memory 206196 kb
Host smart-c4d595f2-2b02-459d-8755-27b116879914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277787976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3277787976
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_alert.1095958994
Short name T247
Test name
Test status
Simulation time 69938489 ps
CPU time 1.16 seconds
Started Mar 10 01:37:09 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 214800 kb
Host smart-d5688100-3c94-4d65-917b-55f5e8d563e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095958994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1095958994
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/288.edn_genbits.2171012009
Short name T11
Test name
Test status
Simulation time 90876951 ps
CPU time 2.51 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 216984 kb
Host smart-85039273-8f6c-47ce-9e9f-ea8480341a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171012009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2171012009
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.152651053
Short name T258
Test name
Test status
Simulation time 24093297 ps
CPU time 0.96 seconds
Started Mar 10 01:36:12 PM PDT 24
Finished Mar 10 01:36:14 PM PDT 24
Peak memory 206232 kb
Host smart-38380355-79d1-4411-8348-d1c372673a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152651053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.152651053
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/43.edn_genbits.3871171096
Short name T274
Test name
Test status
Simulation time 57443861 ps
CPU time 1.38 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:57 PM PDT 24
Peak memory 216764 kb
Host smart-3d20dad6-2d13-4c0f-a690-759dcc388339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871171096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3871171096
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1447944645
Short name T123
Test name
Test status
Simulation time 20415415 ps
CPU time 1.05 seconds
Started Mar 10 01:35:57 PM PDT 24
Finished Mar 10 01:35:58 PM PDT 24
Peak memory 214768 kb
Host smart-408fa231-6676-4e1e-85c3-501c6ae43a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447944645 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1447944645
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/17.edn_alert.3229553690
Short name T180
Test name
Test status
Simulation time 29548541 ps
CPU time 1.35 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 214812 kb
Host smart-bcf17423-78a2-4e07-b136-691b09507d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229553690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3229553690
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1018779974
Short name T207
Test name
Test status
Simulation time 18185508 ps
CPU time 1.05 seconds
Started Mar 10 01:07:03 PM PDT 24
Finished Mar 10 01:07:04 PM PDT 24
Peak memory 206384 kb
Host smart-c9bf573c-13b1-419e-ab96-c160e60a2e07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018779974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1018779974
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.732216277
Short name T211
Test name
Test status
Simulation time 253861826 ps
CPU time 6.01 seconds
Started Mar 10 01:06:59 PM PDT 24
Finished Mar 10 01:07:06 PM PDT 24
Peak memory 206352 kb
Host smart-d0dd8dc6-6252-4d6b-8ffb-9d936d8b3360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732216277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.732216277
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3332477678
Short name T208
Test name
Test status
Simulation time 52266740 ps
CPU time 0.9 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:06 PM PDT 24
Peak memory 206236 kb
Host smart-ef43884e-2f73-4a66-9aae-c5321908b66f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332477678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3332477678
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2928414452
Short name T919
Test name
Test status
Simulation time 118095213 ps
CPU time 1.49 seconds
Started Mar 10 01:07:02 PM PDT 24
Finished Mar 10 01:07:04 PM PDT 24
Peak memory 214800 kb
Host smart-2119cfe4-d7ff-49c0-8a80-fb7601488501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928414452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2928414452
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3621366291
Short name T216
Test name
Test status
Simulation time 15212166 ps
CPU time 0.9 seconds
Started Mar 10 01:07:00 PM PDT 24
Finished Mar 10 01:07:02 PM PDT 24
Peak memory 206380 kb
Host smart-e9f61927-7da3-4144-8281-d83dae640729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621366291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3621366291
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1601863712
Short name T890
Test name
Test status
Simulation time 74724492 ps
CPU time 0.99 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:02 PM PDT 24
Peak memory 206364 kb
Host smart-7f1ad44a-1254-4177-8afc-bc1859418a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601863712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1601863712
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2215275439
Short name T970
Test name
Test status
Simulation time 213149380 ps
CPU time 1.33 seconds
Started Mar 10 01:07:03 PM PDT 24
Finished Mar 10 01:07:04 PM PDT 24
Peak memory 206288 kb
Host smart-d7850efb-f04e-44b4-8288-255674056c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215275439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2215275439
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.889006432
Short name T874
Test name
Test status
Simulation time 80892455 ps
CPU time 1.95 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:03 PM PDT 24
Peak memory 214660 kb
Host smart-230bd6c8-148e-49bf-831f-2ccb936818d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889006432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.889006432
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3030809423
Short name T240
Test name
Test status
Simulation time 96502941 ps
CPU time 2.18 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:08 PM PDT 24
Peak memory 206236 kb
Host smart-c67a9ffc-ecdd-46a6-ab88-9e91cdf298cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030809423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3030809423
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.616431735
Short name T215
Test name
Test status
Simulation time 35509588 ps
CPU time 1.54 seconds
Started Mar 10 01:07:02 PM PDT 24
Finished Mar 10 01:07:04 PM PDT 24
Peak memory 206360 kb
Host smart-1304c243-3fd0-45b7-beb9-05f7be48ac0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616431735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.616431735
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.239838981
Short name T863
Test name
Test status
Simulation time 182442619 ps
CPU time 5.24 seconds
Started Mar 10 01:07:02 PM PDT 24
Finished Mar 10 01:07:08 PM PDT 24
Peak memory 206332 kb
Host smart-9825cb98-d1ab-4947-a0fc-8c5a44f11630
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239838981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.239838981
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2540144157
Short name T939
Test name
Test status
Simulation time 56137383 ps
CPU time 0.96 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:03 PM PDT 24
Peak memory 206352 kb
Host smart-ee41284f-070b-4bf3-b2a2-edd475dd8803
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540144157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2540144157
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2635625151
Short name T940
Test name
Test status
Simulation time 41134437 ps
CPU time 1.15 seconds
Started Mar 10 01:06:58 PM PDT 24
Finished Mar 10 01:06:59 PM PDT 24
Peak memory 214640 kb
Host smart-7ebf73ba-14e3-4df6-bf39-549e7b08e2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635625151 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2635625151
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.837262651
Short name T905
Test name
Test status
Simulation time 40153599 ps
CPU time 0.92 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:03 PM PDT 24
Peak memory 206308 kb
Host smart-ca9a6927-0132-409c-aa10-5c2599e1d4a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837262651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.837262651
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1497107
Short name T950
Test name
Test status
Simulation time 16087331 ps
CPU time 0.8 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 206432 kb
Host smart-ce779bc6-fbf6-4e68-8366-7a3520857be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1497107
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1325499032
Short name T879
Test name
Test status
Simulation time 26046450 ps
CPU time 1.18 seconds
Started Mar 10 01:07:00 PM PDT 24
Finished Mar 10 01:07:01 PM PDT 24
Peak memory 206340 kb
Host smart-92d5a9db-be13-482a-9dbb-8cfb457ded11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325499032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1325499032
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1290006857
Short name T899
Test name
Test status
Simulation time 157545429 ps
CPU time 1.55 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:03 PM PDT 24
Peak memory 214700 kb
Host smart-aee0a5e9-115b-4624-87cd-d9f93f04d1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290006857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1290006857
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4186274113
Short name T925
Test name
Test status
Simulation time 183376919 ps
CPU time 2.51 seconds
Started Mar 10 01:07:01 PM PDT 24
Finished Mar 10 01:07:04 PM PDT 24
Peak memory 206368 kb
Host smart-59c3518c-d1a1-4448-a8f4-140daef01d59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186274113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4186274113
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.226159811
Short name T967
Test name
Test status
Simulation time 118883773 ps
CPU time 0.95 seconds
Started Mar 10 01:07:30 PM PDT 24
Finished Mar 10 01:07:31 PM PDT 24
Peak memory 206416 kb
Host smart-2ef6d2a9-cdf7-4dc0-b5ca-97d648391b7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226159811 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.226159811
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.308670387
Short name T947
Test name
Test status
Simulation time 13584564 ps
CPU time 0.85 seconds
Started Mar 10 01:07:27 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 206276 kb
Host smart-c363066b-ca8c-4fb6-904b-382078bad71f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308670387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.308670387
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2913398662
Short name T948
Test name
Test status
Simulation time 12646421 ps
CPU time 0.89 seconds
Started Mar 10 01:07:27 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 206232 kb
Host smart-a4402a91-ba50-446c-bdc0-115b525f1758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913398662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2913398662
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1392370248
Short name T885
Test name
Test status
Simulation time 42968044 ps
CPU time 0.98 seconds
Started Mar 10 01:07:27 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 206352 kb
Host smart-7362c945-11aa-463e-8bb2-87d1e5ac5414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392370248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1392370248
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3467162315
Short name T946
Test name
Test status
Simulation time 560154643 ps
CPU time 4.22 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 214636 kb
Host smart-c4fa2fbd-1d86-4207-8adb-649c8f1b3611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467162315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3467162315
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.553516953
Short name T927
Test name
Test status
Simulation time 324666952 ps
CPU time 2.41 seconds
Started Mar 10 01:07:29 PM PDT 24
Finished Mar 10 01:07:32 PM PDT 24
Peak memory 206352 kb
Host smart-25f9f528-c4b4-4487-bcb0-302b166c27da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553516953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.553516953
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2719845760
Short name T901
Test name
Test status
Simulation time 35116564 ps
CPU time 0.99 seconds
Started Mar 10 01:07:33 PM PDT 24
Finished Mar 10 01:07:35 PM PDT 24
Peak memory 206780 kb
Host smart-2d50991b-7052-4421-a622-09187f6e9879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719845760 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2719845760
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.655762768
Short name T206
Test name
Test status
Simulation time 30652994 ps
CPU time 0.94 seconds
Started Mar 10 01:07:34 PM PDT 24
Finished Mar 10 01:07:35 PM PDT 24
Peak memory 206272 kb
Host smart-5806820d-db1f-4b1d-8b55-06bc39ea1e20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655762768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.655762768
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2927205559
Short name T854
Test name
Test status
Simulation time 16217929 ps
CPU time 0.9 seconds
Started Mar 10 01:07:29 PM PDT 24
Finished Mar 10 01:07:30 PM PDT 24
Peak memory 206244 kb
Host smart-ad585c11-3c4b-47dc-ace2-dec52a78943a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927205559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2927205559
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3676300293
Short name T908
Test name
Test status
Simulation time 76180648 ps
CPU time 2.83 seconds
Started Mar 10 01:07:29 PM PDT 24
Finished Mar 10 01:07:32 PM PDT 24
Peak memory 214624 kb
Host smart-ec0a7669-1c7d-41fa-adee-6fa85e74acbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676300293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3676300293
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3720112163
Short name T952
Test name
Test status
Simulation time 320915178 ps
CPU time 2.24 seconds
Started Mar 10 01:07:28 PM PDT 24
Finished Mar 10 01:07:30 PM PDT 24
Peak memory 206436 kb
Host smart-d73ec91e-b0c0-45f8-8cdc-a68446bb3a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720112163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3720112163
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2323493170
Short name T966
Test name
Test status
Simulation time 25597638 ps
CPU time 1.26 seconds
Started Mar 10 01:07:41 PM PDT 24
Finished Mar 10 01:07:43 PM PDT 24
Peak memory 214700 kb
Host smart-e954a402-94b5-40ca-aec2-2688ce008855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323493170 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2323493170
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2571413330
Short name T924
Test name
Test status
Simulation time 51309715 ps
CPU time 0.93 seconds
Started Mar 10 01:07:39 PM PDT 24
Finished Mar 10 01:07:40 PM PDT 24
Peak memory 206180 kb
Host smart-403f5374-3cf2-47ef-8c19-8aaa5b0f0096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571413330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2571413330
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.181082099
Short name T902
Test name
Test status
Simulation time 37645038 ps
CPU time 0.84 seconds
Started Mar 10 01:07:34 PM PDT 24
Finished Mar 10 01:07:35 PM PDT 24
Peak memory 206276 kb
Host smart-40f73ac7-efbf-4ee5-9107-edee0338afd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181082099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.181082099
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4098167352
Short name T883
Test name
Test status
Simulation time 257613342 ps
CPU time 1.16 seconds
Started Mar 10 01:07:38 PM PDT 24
Finished Mar 10 01:07:40 PM PDT 24
Peak memory 206300 kb
Host smart-b411f216-9653-4652-bf1f-b71fc8c419a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098167352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4098167352
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3097343003
Short name T851
Test name
Test status
Simulation time 906352669 ps
CPU time 2.44 seconds
Started Mar 10 01:07:35 PM PDT 24
Finished Mar 10 01:07:38 PM PDT 24
Peak memory 214616 kb
Host smart-d50ef181-da85-4594-8850-39900541766c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097343003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3097343003
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.581211743
Short name T911
Test name
Test status
Simulation time 113758955 ps
CPU time 1.43 seconds
Started Mar 10 01:07:39 PM PDT 24
Finished Mar 10 01:07:41 PM PDT 24
Peak memory 206344 kb
Host smart-53c46e60-b509-45be-8e73-e75aea3582fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581211743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.581211743
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2190747244
Short name T852
Test name
Test status
Simulation time 98351653 ps
CPU time 1.11 seconds
Started Mar 10 01:07:38 PM PDT 24
Finished Mar 10 01:07:39 PM PDT 24
Peak memory 214708 kb
Host smart-2d8ccdf9-81d6-46cd-a4e4-ed2e1a7b6fef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190747244 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2190747244
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3846292046
Short name T209
Test name
Test status
Simulation time 13215251 ps
CPU time 0.93 seconds
Started Mar 10 01:07:43 PM PDT 24
Finished Mar 10 01:07:44 PM PDT 24
Peak memory 206320 kb
Host smart-107ebc9f-61e0-490a-8950-407aeff82b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846292046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3846292046
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4031232793
Short name T944
Test name
Test status
Simulation time 15680519 ps
CPU time 0.89 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:41 PM PDT 24
Peak memory 206376 kb
Host smart-4c61c60f-a23c-4585-b12c-88104382439f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031232793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4031232793
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.299429658
Short name T201
Test name
Test status
Simulation time 74886161 ps
CPU time 1.01 seconds
Started Mar 10 01:07:38 PM PDT 24
Finished Mar 10 01:07:39 PM PDT 24
Peak memory 206304 kb
Host smart-83c4af4f-84db-4444-b600-bda90eee0124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299429658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.299429658
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2654179885
Short name T931
Test name
Test status
Simulation time 326334890 ps
CPU time 3.26 seconds
Started Mar 10 01:07:39 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 214568 kb
Host smart-00e07f6f-cb22-43d4-984b-2a1b15fc2b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654179885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2654179885
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1523319585
Short name T934
Test name
Test status
Simulation time 34627954 ps
CPU time 2.12 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 214580 kb
Host smart-daa60727-5ba4-4a3e-8f61-35ed854be779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523319585 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1523319585
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3865470019
Short name T229
Test name
Test status
Simulation time 29023406 ps
CPU time 0.96 seconds
Started Mar 10 01:07:39 PM PDT 24
Finished Mar 10 01:07:41 PM PDT 24
Peak memory 206376 kb
Host smart-7594a532-3d13-4960-b8a1-12d114791bb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865470019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3865470019
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.376617347
Short name T849
Test name
Test status
Simulation time 161085845 ps
CPU time 0.92 seconds
Started Mar 10 01:07:41 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 206136 kb
Host smart-d4626514-090b-4b04-af5f-e3f302aae7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376617347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.376617347
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.263960609
Short name T956
Test name
Test status
Simulation time 26953117 ps
CPU time 1.08 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:41 PM PDT 24
Peak memory 206456 kb
Host smart-68ca6cc7-22d6-4481-bdfd-9c7b7e3448d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263960609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.263960609
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2456405588
Short name T932
Test name
Test status
Simulation time 123624559 ps
CPU time 4.19 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:50 PM PDT 24
Peak memory 214596 kb
Host smart-b74c88af-9a93-4a9f-ba60-60e929ae2fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456405588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2456405588
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1407356946
Short name T953
Test name
Test status
Simulation time 62204100 ps
CPU time 1.26 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 214572 kb
Host smart-dfd83dc8-2bb9-4ea1-a489-1831a9512a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407356946 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1407356946
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3334694776
Short name T942
Test name
Test status
Simulation time 20909245 ps
CPU time 0.83 seconds
Started Mar 10 01:07:43 PM PDT 24
Finished Mar 10 01:07:44 PM PDT 24
Peak memory 206200 kb
Host smart-a43ccef0-63eb-45d6-95a7-ff5a4b094680
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334694776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3334694776
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.615744988
Short name T884
Test name
Test status
Simulation time 15447687 ps
CPU time 0.88 seconds
Started Mar 10 01:07:41 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 206320 kb
Host smart-916686f8-356b-4d4b-9c60-c939fb6798fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615744988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.615744988
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1873409089
Short name T875
Test name
Test status
Simulation time 52013329 ps
CPU time 0.98 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 206344 kb
Host smart-380191ad-c2cc-4b50-b0fe-2dc0ca4820da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873409089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1873409089
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.976466701
Short name T957
Test name
Test status
Simulation time 241690123 ps
CPU time 3.94 seconds
Started Mar 10 01:07:42 PM PDT 24
Finished Mar 10 01:07:46 PM PDT 24
Peak memory 214776 kb
Host smart-7273af0d-4f12-44e4-9241-bf3b8a18cf1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976466701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.976466701
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.370149947
Short name T964
Test name
Test status
Simulation time 108225349 ps
CPU time 1.65 seconds
Started Mar 10 01:07:38 PM PDT 24
Finished Mar 10 01:07:39 PM PDT 24
Peak memory 206412 kb
Host smart-9c630178-29ae-4a18-828e-c813487dc17e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370149947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.370149947
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1481542659
Short name T853
Test name
Test status
Simulation time 22247596 ps
CPU time 1.37 seconds
Started Mar 10 01:07:42 PM PDT 24
Finished Mar 10 01:07:43 PM PDT 24
Peak memory 214616 kb
Host smart-48d59d57-5d39-4e85-85ca-7fe0bbd90711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481542659 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1481542659
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4078470610
Short name T213
Test name
Test status
Simulation time 19296816 ps
CPU time 0.88 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:47 PM PDT 24
Peak memory 206312 kb
Host smart-8b78d32d-c238-4013-a530-92e311dbc668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078470610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4078470610
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1012891354
Short name T945
Test name
Test status
Simulation time 25773494 ps
CPU time 0.86 seconds
Started Mar 10 01:07:40 PM PDT 24
Finished Mar 10 01:07:41 PM PDT 24
Peak memory 206304 kb
Host smart-b70d12d2-4704-430b-b7e1-4e382d5b416f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012891354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1012891354
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2093455812
Short name T877
Test name
Test status
Simulation time 32555628 ps
CPU time 1.39 seconds
Started Mar 10 01:07:44 PM PDT 24
Finished Mar 10 01:07:46 PM PDT 24
Peak memory 206360 kb
Host smart-260634c9-1ee9-40a2-8f2f-5a665a096e31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093455812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2093455812
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2448676110
Short name T886
Test name
Test status
Simulation time 618980935 ps
CPU time 3.18 seconds
Started Mar 10 01:07:39 PM PDT 24
Finished Mar 10 01:07:42 PM PDT 24
Peak memory 214672 kb
Host smart-2157a72d-20b3-46d9-a8f6-f3b9d31fe7da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448676110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2448676110
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2235400679
Short name T239
Test name
Test status
Simulation time 148634308 ps
CPU time 2.37 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 206332 kb
Host smart-3e2893d8-e3d1-4081-89f8-8b588ec07b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235400679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2235400679
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2439667482
Short name T968
Test name
Test status
Simulation time 52153840 ps
CPU time 1.3 seconds
Started Mar 10 01:07:49 PM PDT 24
Finished Mar 10 01:07:51 PM PDT 24
Peak memory 214644 kb
Host smart-2e039107-fda6-44ec-a23a-4d562e78ca48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439667482 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2439667482
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.81078862
Short name T892
Test name
Test status
Simulation time 20885578 ps
CPU time 0.85 seconds
Started Mar 10 01:07:47 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 206392 kb
Host smart-9141fa80-d8a4-4194-972c-77b41636610b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81078862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.81078862
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3934155577
Short name T936
Test name
Test status
Simulation time 19975153 ps
CPU time 0.8 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 206256 kb
Host smart-45063a57-b87b-4bef-b58f-b46aa4c47921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934155577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3934155577
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1003940491
Short name T205
Test name
Test status
Simulation time 224302035 ps
CPU time 1.23 seconds
Started Mar 10 01:07:48 PM PDT 24
Finished Mar 10 01:07:50 PM PDT 24
Peak memory 206388 kb
Host smart-57a5710b-7d0d-4e4d-b0d2-bf0035a7780a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003940491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1003940491
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.87361141
Short name T914
Test name
Test status
Simulation time 577238657 ps
CPU time 2.36 seconds
Started Mar 10 01:07:47 PM PDT 24
Finished Mar 10 01:07:49 PM PDT 24
Peak memory 214572 kb
Host smart-fbe99e67-8cfa-4435-a74c-b0cc439581ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87361141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.87361141
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.499998156
Short name T920
Test name
Test status
Simulation time 40416170 ps
CPU time 1.53 seconds
Started Mar 10 01:07:46 PM PDT 24
Finished Mar 10 01:07:47 PM PDT 24
Peak memory 206400 kb
Host smart-6345031a-585e-442c-bdc0-d52434b4995f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499998156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.499998156
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1773860107
Short name T961
Test name
Test status
Simulation time 74409450 ps
CPU time 1.56 seconds
Started Mar 10 01:07:50 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 214620 kb
Host smart-5abc0ed2-135d-4693-bfcd-b831932809fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773860107 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1773860107
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1133317278
Short name T230
Test name
Test status
Simulation time 53319063 ps
CPU time 0.89 seconds
Started Mar 10 01:07:50 PM PDT 24
Finished Mar 10 01:07:51 PM PDT 24
Peak memory 206296 kb
Host smart-e99f9a46-a889-4c7f-a4f8-6644e5134690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133317278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1133317278
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2773866058
Short name T960
Test name
Test status
Simulation time 25606739 ps
CPU time 0.87 seconds
Started Mar 10 01:07:48 PM PDT 24
Finished Mar 10 01:07:49 PM PDT 24
Peak memory 206392 kb
Host smart-649c6535-3dca-439d-bb67-4d2c97fbc2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773866058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2773866058
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1119779718
Short name T923
Test name
Test status
Simulation time 17461152 ps
CPU time 0.97 seconds
Started Mar 10 01:07:47 PM PDT 24
Finished Mar 10 01:07:48 PM PDT 24
Peak memory 206292 kb
Host smart-d922177d-0c6c-4a62-8b98-b825915b14b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119779718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1119779718
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2987765605
Short name T859
Test name
Test status
Simulation time 175802578 ps
CPU time 1.71 seconds
Started Mar 10 01:07:48 PM PDT 24
Finished Mar 10 01:07:50 PM PDT 24
Peak memory 214624 kb
Host smart-e8fdbb8c-3c7b-4003-ac82-8a8304d19c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987765605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2987765605
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.112008491
Short name T231
Test name
Test status
Simulation time 54280943 ps
CPU time 1.4 seconds
Started Mar 10 01:07:49 PM PDT 24
Finished Mar 10 01:07:51 PM PDT 24
Peak memory 206420 kb
Host smart-b1011e4e-ff69-4cc3-98e2-8dbd54d9da21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112008491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.112008491
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1290702742
Short name T848
Test name
Test status
Simulation time 19711096 ps
CPU time 1.01 seconds
Started Mar 10 01:07:48 PM PDT 24
Finished Mar 10 01:07:49 PM PDT 24
Peak memory 206444 kb
Host smart-44730405-dce4-41e8-8d94-c62bad621087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290702742 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1290702742
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.717579885
Short name T963
Test name
Test status
Simulation time 15923627 ps
CPU time 0.89 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206364 kb
Host smart-5673616f-791b-4343-a4d3-6ad1ab952df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717579885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.717579885
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2704718320
Short name T217
Test name
Test status
Simulation time 46867448 ps
CPU time 1.14 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206344 kb
Host smart-ada1fdb5-925c-4591-bfb7-8b58442b708f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704718320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2704718320
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2551379534
Short name T845
Test name
Test status
Simulation time 50728223 ps
CPU time 1.92 seconds
Started Mar 10 01:07:49 PM PDT 24
Finished Mar 10 01:07:51 PM PDT 24
Peak memory 214548 kb
Host smart-5ec4afdd-04b5-4a24-a542-f47dd130e598
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551379534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2551379534
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3785464833
Short name T958
Test name
Test status
Simulation time 324797662 ps
CPU time 2.29 seconds
Started Mar 10 01:07:49 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206312 kb
Host smart-42c35042-19d9-4a6d-af6b-432915153c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785464833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3785464833
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3719876277
Short name T921
Test name
Test status
Simulation time 119562633 ps
CPU time 0.94 seconds
Started Mar 10 01:07:06 PM PDT 24
Finished Mar 10 01:07:07 PM PDT 24
Peak memory 206316 kb
Host smart-2485089c-2e46-4f43-b394-00dfcad82a69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719876277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3719876277
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2382490220
Short name T893
Test name
Test status
Simulation time 57378882 ps
CPU time 3.39 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:08 PM PDT 24
Peak memory 206376 kb
Host smart-71c14348-027c-4a90-b4f8-135aad5a456a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382490220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2382490220
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2182143589
Short name T198
Test name
Test status
Simulation time 170105671 ps
CPU time 0.83 seconds
Started Mar 10 01:07:05 PM PDT 24
Finished Mar 10 01:07:07 PM PDT 24
Peak memory 206312 kb
Host smart-634af2e1-a1e2-484d-8b99-a7bdf0ecb827
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182143589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2182143589
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3141892492
Short name T864
Test name
Test status
Simulation time 188391614 ps
CPU time 1.11 seconds
Started Mar 10 01:07:10 PM PDT 24
Finished Mar 10 01:07:11 PM PDT 24
Peak memory 215968 kb
Host smart-551d371f-a6f0-492c-b0cc-7a60058922fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141892492 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3141892492
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.718392349
Short name T916
Test name
Test status
Simulation time 81796775 ps
CPU time 0.86 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 206356 kb
Host smart-e3bd2224-8fe8-4d7f-aef1-69def76809c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718392349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.718392349
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2938766048
Short name T928
Test name
Test status
Simulation time 49736171 ps
CPU time 0.79 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 206092 kb
Host smart-9572d5b6-20a2-49ff-b9ef-4173751ddaf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938766048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2938766048
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2825676318
Short name T898
Test name
Test status
Simulation time 22758858 ps
CPU time 1.1 seconds
Started Mar 10 01:07:06 PM PDT 24
Finished Mar 10 01:07:07 PM PDT 24
Peak memory 206352 kb
Host smart-5cdb72bc-406b-4d4a-8ab8-91fc2d5af11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825676318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2825676318
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.75595687
Short name T938
Test name
Test status
Simulation time 63031919 ps
CPU time 1.54 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:06 PM PDT 24
Peak memory 214552 kb
Host smart-b3b0a140-e73a-4996-bd3f-1239ca29f92d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75595687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.75595687
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1814585327
Short name T232
Test name
Test status
Simulation time 99927833 ps
CPU time 1.59 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:07 PM PDT 24
Peak memory 206404 kb
Host smart-8af32a8d-7b52-49fa-bf2a-1aea56c26e87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814585327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1814585327
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2173879458
Short name T969
Test name
Test status
Simulation time 15961952 ps
CPU time 0.91 seconds
Started Mar 10 01:07:52 PM PDT 24
Finished Mar 10 01:07:53 PM PDT 24
Peak memory 206300 kb
Host smart-ea78ce59-808b-483c-92cb-758ef2578784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173879458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2173879458
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4000078248
Short name T862
Test name
Test status
Simulation time 18984314 ps
CPU time 0.83 seconds
Started Mar 10 01:07:53 PM PDT 24
Finished Mar 10 01:07:54 PM PDT 24
Peak memory 206208 kb
Host smart-1e0ad26f-7e38-4773-ae74-77ce436cd59a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000078248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4000078248
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2269360949
Short name T912
Test name
Test status
Simulation time 26425109 ps
CPU time 0.86 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206352 kb
Host smart-3494c988-9601-458c-9ca8-4c1320bb2885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269360949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2269360949
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2563978248
Short name T880
Test name
Test status
Simulation time 21349941 ps
CPU time 0.86 seconds
Started Mar 10 01:07:52 PM PDT 24
Finished Mar 10 01:07:53 PM PDT 24
Peak memory 206320 kb
Host smart-025990f9-d8ce-487c-b17e-40c715edf2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563978248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2563978248
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4118532019
Short name T876
Test name
Test status
Simulation time 96328441 ps
CPU time 0.79 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206160 kb
Host smart-9ba81a40-00a7-4020-b4c9-7594eb793fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118532019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4118532019
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3706459390
Short name T843
Test name
Test status
Simulation time 11960257 ps
CPU time 0.83 seconds
Started Mar 10 01:07:50 PM PDT 24
Finished Mar 10 01:07:51 PM PDT 24
Peak memory 206252 kb
Host smart-81ab854a-903d-4c41-9665-d743e805472a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706459390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3706459390
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.837291230
Short name T907
Test name
Test status
Simulation time 14904257 ps
CPU time 0.9 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206376 kb
Host smart-577fb6af-6c48-47bd-b416-19609ae10eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837291230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.837291230
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1112008317
Short name T951
Test name
Test status
Simulation time 13220704 ps
CPU time 0.86 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206248 kb
Host smart-7688b635-ed7b-462e-8b0d-16c296500911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112008317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1112008317
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2707408272
Short name T888
Test name
Test status
Simulation time 31451316 ps
CPU time 0.83 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206328 kb
Host smart-4732a092-f34e-4654-8c42-2202abe839f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707408272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2707408272
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2584620087
Short name T915
Test name
Test status
Simulation time 34236519 ps
CPU time 0.78 seconds
Started Mar 10 01:07:52 PM PDT 24
Finished Mar 10 01:07:53 PM PDT 24
Peak memory 206192 kb
Host smart-87326e3f-08bf-4693-9551-a927b16fb2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584620087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2584620087
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3139608071
Short name T203
Test name
Test status
Simulation time 51899239 ps
CPU time 1.14 seconds
Started Mar 10 01:07:20 PM PDT 24
Finished Mar 10 01:07:22 PM PDT 24
Peak memory 206296 kb
Host smart-daa56021-e56e-48af-a72f-a09469f3a0f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139608071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3139608071
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1797814050
Short name T857
Test name
Test status
Simulation time 348531857 ps
CPU time 3.57 seconds
Started Mar 10 01:07:11 PM PDT 24
Finished Mar 10 01:07:15 PM PDT 24
Peak memory 206324 kb
Host smart-656930b7-b81c-4daa-abda-d7647eb3f6d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797814050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1797814050
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1089970235
Short name T214
Test name
Test status
Simulation time 48135615 ps
CPU time 0.85 seconds
Started Mar 10 01:07:09 PM PDT 24
Finished Mar 10 01:07:10 PM PDT 24
Peak memory 206220 kb
Host smart-03639232-dbbb-4e86-b755-8af4fd2019ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089970235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1089970235
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2908014551
Short name T930
Test name
Test status
Simulation time 29956171 ps
CPU time 2.02 seconds
Started Mar 10 01:07:12 PM PDT 24
Finished Mar 10 01:07:15 PM PDT 24
Peak memory 214652 kb
Host smart-047c8ed8-c922-46b1-87b6-83a449303f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908014551 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2908014551
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1706839463
Short name T943
Test name
Test status
Simulation time 49504674 ps
CPU time 0.89 seconds
Started Mar 10 01:07:13 PM PDT 24
Finished Mar 10 01:07:14 PM PDT 24
Peak memory 206312 kb
Host smart-6d005996-b5ae-4b64-8d91-bb846b68cf97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706839463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1706839463
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.523120431
Short name T918
Test name
Test status
Simulation time 49655228 ps
CPU time 0.82 seconds
Started Mar 10 01:07:11 PM PDT 24
Finished Mar 10 01:07:12 PM PDT 24
Peak memory 206324 kb
Host smart-e8c08243-93d2-4bb8-9a5f-fdbeeb48db06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523120431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.523120431
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1235405635
Short name T218
Test name
Test status
Simulation time 54961659 ps
CPU time 1.12 seconds
Started Mar 10 01:07:10 PM PDT 24
Finished Mar 10 01:07:11 PM PDT 24
Peak memory 206344 kb
Host smart-67ef7528-d488-49ec-a03c-0bd0e172364c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235405635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1235405635
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4117855446
Short name T882
Test name
Test status
Simulation time 72974425 ps
CPU time 2.45 seconds
Started Mar 10 01:07:15 PM PDT 24
Finished Mar 10 01:07:17 PM PDT 24
Peak memory 214624 kb
Host smart-53b48010-ed68-4c24-b22d-cc2f8471f779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117855446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4117855446
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3203461310
Short name T244
Test name
Test status
Simulation time 314977452 ps
CPU time 2.45 seconds
Started Mar 10 01:07:13 PM PDT 24
Finished Mar 10 01:07:15 PM PDT 24
Peak memory 206380 kb
Host smart-4397e3ac-1b03-437d-8495-de48377adf6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203461310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3203461310
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2638586774
Short name T869
Test name
Test status
Simulation time 20341969 ps
CPU time 0.87 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206324 kb
Host smart-0fc5e933-8f90-4f49-be93-7d47829d9c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638586774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2638586774
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2260076879
Short name T913
Test name
Test status
Simulation time 11825252 ps
CPU time 0.8 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206320 kb
Host smart-e46e8bf7-5dc7-43da-b500-279e130445d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260076879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2260076879
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1104720882
Short name T903
Test name
Test status
Simulation time 23000547 ps
CPU time 0.92 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206364 kb
Host smart-51bf6237-b28a-43d0-8be3-10ba50b3e0c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104720882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1104720882
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.305493397
Short name T868
Test name
Test status
Simulation time 14159003 ps
CPU time 0.89 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206252 kb
Host smart-f6cf605b-8a07-40f8-a432-40b16ff12f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305493397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.305493397
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.66325906
Short name T865
Test name
Test status
Simulation time 22974869 ps
CPU time 0.85 seconds
Started Mar 10 01:07:53 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206228 kb
Host smart-3229e00d-a024-4785-a711-e6cecf19db4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66325906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.66325906
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.975477742
Short name T856
Test name
Test status
Simulation time 50083616 ps
CPU time 0.81 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206200 kb
Host smart-6983ffd3-ac41-4259-88bb-cc5739c58126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975477742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.975477742
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.219571260
Short name T926
Test name
Test status
Simulation time 43486643 ps
CPU time 0.86 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:07:59 PM PDT 24
Peak memory 206372 kb
Host smart-6a8d657b-c057-45d6-a9e8-db88c2c865df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219571260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.219571260
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1238455664
Short name T860
Test name
Test status
Simulation time 22461375 ps
CPU time 0.82 seconds
Started Mar 10 01:07:51 PM PDT 24
Finished Mar 10 01:07:52 PM PDT 24
Peak memory 206324 kb
Host smart-b79ed56c-0b49-49c7-8fdf-8f27ef237c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238455664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1238455664
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.91126583
Short name T847
Test name
Test status
Simulation time 75859838 ps
CPU time 0.85 seconds
Started Mar 10 01:07:54 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206136 kb
Host smart-76d9ff29-e337-4e06-b60a-208e702b3b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91126583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.91126583
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1522622385
Short name T962
Test name
Test status
Simulation time 26194770 ps
CPU time 0.83 seconds
Started Mar 10 01:07:53 PM PDT 24
Finished Mar 10 01:07:55 PM PDT 24
Peak memory 206076 kb
Host smart-1d5f76e9-0fd6-4536-bc1d-fd7a4cf6ea93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522622385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1522622385
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3244851594
Short name T212
Test name
Test status
Simulation time 53811789 ps
CPU time 1.65 seconds
Started Mar 10 01:07:17 PM PDT 24
Finished Mar 10 01:07:19 PM PDT 24
Peak memory 206332 kb
Host smart-778a3ec0-bd81-423e-9079-fe2d8ecbfa96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244851594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3244851594
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.787227940
Short name T867
Test name
Test status
Simulation time 58994317 ps
CPU time 3.23 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:22 PM PDT 24
Peak memory 206300 kb
Host smart-fd9051d8-293e-440e-b088-abe63f321cc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787227940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.787227940
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.636661486
Short name T959
Test name
Test status
Simulation time 49661846 ps
CPU time 0.94 seconds
Started Mar 10 01:07:15 PM PDT 24
Finished Mar 10 01:07:16 PM PDT 24
Peak memory 206300 kb
Host smart-0093c386-ffe8-4402-ab7f-2b90589d3892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636661486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.636661486
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.800917896
Short name T917
Test name
Test status
Simulation time 27668751 ps
CPU time 1.49 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:20 PM PDT 24
Peak memory 214656 kb
Host smart-7506f2e3-8629-4603-afb9-c89c9b36a490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800917896 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.800917896
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2457198692
Short name T878
Test name
Test status
Simulation time 16715473 ps
CPU time 0.95 seconds
Started Mar 10 01:07:21 PM PDT 24
Finished Mar 10 01:07:22 PM PDT 24
Peak memory 206320 kb
Host smart-3a474d8c-7ac7-438a-b301-d4518112844e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457198692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2457198692
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3533687165
Short name T866
Test name
Test status
Simulation time 12872044 ps
CPU time 0.87 seconds
Started Mar 10 01:07:11 PM PDT 24
Finished Mar 10 01:07:12 PM PDT 24
Peak memory 206308 kb
Host smart-be332004-812e-4ba4-9841-0cd805e8f3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533687165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3533687165
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3760579157
Short name T871
Test name
Test status
Simulation time 17287323 ps
CPU time 1.13 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:20 PM PDT 24
Peak memory 206404 kb
Host smart-0e9f7078-966d-4e84-8122-fc9d6f9b0b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760579157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3760579157
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3674249543
Short name T904
Test name
Test status
Simulation time 77140009 ps
CPU time 2.86 seconds
Started Mar 10 01:07:12 PM PDT 24
Finished Mar 10 01:07:15 PM PDT 24
Peak memory 214648 kb
Host smart-f0dfe64d-94da-43ef-9b50-3002e6544bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674249543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3674249543
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.160910649
Short name T241
Test name
Test status
Simulation time 138625413 ps
CPU time 3 seconds
Started Mar 10 01:07:11 PM PDT 24
Finished Mar 10 01:07:14 PM PDT 24
Peak memory 206376 kb
Host smart-aa7705cc-c106-40ac-b58e-2f1a758ff173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160910649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.160910649
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3885426156
Short name T929
Test name
Test status
Simulation time 14769420 ps
CPU time 0.9 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:07:59 PM PDT 24
Peak memory 206356 kb
Host smart-bc2b73b2-1d8b-4bca-90f0-b0364c89d63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885426156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3885426156
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3509484560
Short name T855
Test name
Test status
Simulation time 20862361 ps
CPU time 0.79 seconds
Started Mar 10 01:07:52 PM PDT 24
Finished Mar 10 01:07:53 PM PDT 24
Peak memory 206208 kb
Host smart-d6795419-2723-4a7d-b110-eb2d19193923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509484560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3509484560
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1581281605
Short name T858
Test name
Test status
Simulation time 189580055 ps
CPU time 0.94 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:07:59 PM PDT 24
Peak memory 206208 kb
Host smart-980ab6e4-a0c0-454a-be26-a955d99b2185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581281605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1581281605
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1874331605
Short name T842
Test name
Test status
Simulation time 72209556 ps
CPU time 0.87 seconds
Started Mar 10 01:07:55 PM PDT 24
Finished Mar 10 01:07:57 PM PDT 24
Peak memory 206348 kb
Host smart-860445d5-9728-4fca-babe-80735c42aebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874331605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1874331605
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4014944023
Short name T954
Test name
Test status
Simulation time 20103407 ps
CPU time 0.76 seconds
Started Mar 10 01:07:56 PM PDT 24
Finished Mar 10 01:07:57 PM PDT 24
Peak memory 206160 kb
Host smart-f4e9e3fa-a9fa-4a43-9258-2bbbb41d8a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014944023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4014944023
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1223940073
Short name T891
Test name
Test status
Simulation time 45252175 ps
CPU time 0.84 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:07:58 PM PDT 24
Peak memory 206364 kb
Host smart-3de938ef-0eaf-4247-bfb2-313e48e3ff79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223940073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1223940073
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2069409558
Short name T881
Test name
Test status
Simulation time 27156606 ps
CPU time 0.88 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:07 PM PDT 24
Peak memory 206404 kb
Host smart-8092548a-2c9e-4233-869d-93a2e094df37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069409558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2069409558
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.451696790
Short name T971
Test name
Test status
Simulation time 10724339 ps
CPU time 0.83 seconds
Started Mar 10 01:07:59 PM PDT 24
Finished Mar 10 01:08:00 PM PDT 24
Peak memory 206304 kb
Host smart-d4067c58-88b5-4f44-a717-43d4e04ebbd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451696790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.451696790
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2164181440
Short name T895
Test name
Test status
Simulation time 111937338 ps
CPU time 0.8 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:07:58 PM PDT 24
Peak memory 206116 kb
Host smart-e14ffc0d-e815-4dcd-a59f-c75d58ed306d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164181440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2164181440
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2440051153
Short name T861
Test name
Test status
Simulation time 23022399 ps
CPU time 0.82 seconds
Started Mar 10 01:08:00 PM PDT 24
Finished Mar 10 01:08:01 PM PDT 24
Peak memory 206360 kb
Host smart-ffe40c6e-6317-4639-8893-92a54a66b551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440051153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2440051153
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3539447152
Short name T846
Test name
Test status
Simulation time 27721868 ps
CPU time 1.75 seconds
Started Mar 10 01:07:22 PM PDT 24
Finished Mar 10 01:07:24 PM PDT 24
Peak memory 214596 kb
Host smart-25add9d0-9cd6-41dc-9048-9c1f8fdba77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539447152 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3539447152
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1911190667
Short name T210
Test name
Test status
Simulation time 14514983 ps
CPU time 0.88 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:20 PM PDT 24
Peak memory 206328 kb
Host smart-a1bf68b9-df22-46bf-97cb-573b2d1be5f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911190667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1911190667
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1453273587
Short name T896
Test name
Test status
Simulation time 19781008 ps
CPU time 0.89 seconds
Started Mar 10 01:07:16 PM PDT 24
Finished Mar 10 01:07:17 PM PDT 24
Peak memory 206256 kb
Host smart-40be69bb-da37-4c06-b248-b7133c19b8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453273587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1453273587
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4250871258
Short name T897
Test name
Test status
Simulation time 43143193 ps
CPU time 1.09 seconds
Started Mar 10 01:07:16 PM PDT 24
Finished Mar 10 01:07:18 PM PDT 24
Peak memory 206444 kb
Host smart-093cb2d2-131f-4798-94b5-abc01b2ff37e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250871258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4250871258
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1434372372
Short name T906
Test name
Test status
Simulation time 145425905 ps
CPU time 3.57 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:22 PM PDT 24
Peak memory 214840 kb
Host smart-1b491070-07b0-4a4b-acac-71b86232e0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434372372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1434372372
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.528555842
Short name T955
Test name
Test status
Simulation time 206460257 ps
CPU time 2.35 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:21 PM PDT 24
Peak memory 206380 kb
Host smart-7102fe0a-f9e2-41e4-85ab-902043f6a0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528555842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.528555842
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.12886607
Short name T872
Test name
Test status
Simulation time 72041543 ps
CPU time 1.09 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:25 PM PDT 24
Peak memory 214696 kb
Host smart-a38d6931-9db2-488a-98ef-cfc871b00981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886607 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.12886607
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2267995197
Short name T873
Test name
Test status
Simulation time 32000797 ps
CPU time 0.97 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:19 PM PDT 24
Peak memory 206272 kb
Host smart-ddf4de34-e0fb-45d8-8321-e501348b2762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267995197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2267995197
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1557877336
Short name T887
Test name
Test status
Simulation time 13873280 ps
CPU time 0.88 seconds
Started Mar 10 01:07:19 PM PDT 24
Finished Mar 10 01:07:20 PM PDT 24
Peak memory 206352 kb
Host smart-6c8991a3-0a07-4321-96d2-d33b6f5a5e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557877336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1557877336
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2356543044
Short name T200
Test name
Test status
Simulation time 41837150 ps
CPU time 1.48 seconds
Started Mar 10 01:07:20 PM PDT 24
Finished Mar 10 01:07:21 PM PDT 24
Peak memory 206424 kb
Host smart-ebb52d26-c5e2-40ee-a927-d1e797095847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356543044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2356543044
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3208736490
Short name T889
Test name
Test status
Simulation time 1891492379 ps
CPU time 4.78 seconds
Started Mar 10 01:07:16 PM PDT 24
Finished Mar 10 01:07:22 PM PDT 24
Peak memory 218320 kb
Host smart-2ece296f-ae65-4bc9-858a-f6bf3f787db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208736490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3208736490
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.757185656
Short name T937
Test name
Test status
Simulation time 146746833 ps
CPU time 2.12 seconds
Started Mar 10 01:07:24 PM PDT 24
Finished Mar 10 01:07:26 PM PDT 24
Peak memory 206320 kb
Host smart-13a3d2aa-28ab-4604-a577-23954367ec9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757185656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.757185656
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2813222324
Short name T922
Test name
Test status
Simulation time 30631935 ps
CPU time 1.97 seconds
Started Mar 10 01:07:21 PM PDT 24
Finished Mar 10 01:07:23 PM PDT 24
Peak memory 214700 kb
Host smart-7dc34707-d931-4330-96bf-2778fb0cf9e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813222324 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2813222324
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2047881909
Short name T197
Test name
Test status
Simulation time 40245138 ps
CPU time 0.85 seconds
Started Mar 10 01:07:26 PM PDT 24
Finished Mar 10 01:07:27 PM PDT 24
Peak memory 206324 kb
Host smart-1a1c5b06-1f1c-44f7-9959-7a04da36ad82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047881909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2047881909
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3217242111
Short name T935
Test name
Test status
Simulation time 43257390 ps
CPU time 0.8 seconds
Started Mar 10 01:07:18 PM PDT 24
Finished Mar 10 01:07:19 PM PDT 24
Peak memory 206352 kb
Host smart-ae71c70a-876e-4aba-8923-a4a1686be2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217242111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3217242111
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3171299050
Short name T219
Test name
Test status
Simulation time 56766416 ps
CPU time 1.34 seconds
Started Mar 10 01:07:22 PM PDT 24
Finished Mar 10 01:07:23 PM PDT 24
Peak memory 206352 kb
Host smart-6fa70c78-d9a3-4ca8-8665-92cbe8e0dbe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171299050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3171299050
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2771746798
Short name T894
Test name
Test status
Simulation time 860750989 ps
CPU time 2.48 seconds
Started Mar 10 01:07:21 PM PDT 24
Finished Mar 10 01:07:23 PM PDT 24
Peak memory 214664 kb
Host smart-a0465bba-b820-4cb6-8e84-873aec3ac963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771746798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2771746798
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2453985473
Short name T242
Test name
Test status
Simulation time 91006121 ps
CPU time 1.79 seconds
Started Mar 10 01:07:19 PM PDT 24
Finished Mar 10 01:07:21 PM PDT 24
Peak memory 206372 kb
Host smart-ffeca320-cef8-4826-946a-8245b9d7e03f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453985473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2453985473
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3253677652
Short name T933
Test name
Test status
Simulation time 27343356 ps
CPU time 1.82 seconds
Started Mar 10 01:07:27 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 214644 kb
Host smart-6ee05ca2-02a9-4897-afab-447df083a6df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253677652 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3253677652
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.935233669
Short name T870
Test name
Test status
Simulation time 22793366 ps
CPU time 0.83 seconds
Started Mar 10 01:07:26 PM PDT 24
Finished Mar 10 01:07:27 PM PDT 24
Peak memory 206324 kb
Host smart-4ae6106a-752f-423b-9cf2-1fe6fe5139a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935233669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.935233669
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2476209942
Short name T909
Test name
Test status
Simulation time 153911556 ps
CPU time 0.95 seconds
Started Mar 10 01:07:27 PM PDT 24
Finished Mar 10 01:07:28 PM PDT 24
Peak memory 206148 kb
Host smart-c1517a4f-257d-48d3-806e-c362dc579b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476209942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2476209942
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2988062119
Short name T965
Test name
Test status
Simulation time 32381689 ps
CPU time 0.93 seconds
Started Mar 10 01:07:28 PM PDT 24
Finished Mar 10 01:07:29 PM PDT 24
Peak memory 206292 kb
Host smart-ad6c6a74-563c-4e13-adfe-e296dcb6f55b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988062119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2988062119
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.654134893
Short name T850
Test name
Test status
Simulation time 492666445 ps
CPU time 3.84 seconds
Started Mar 10 01:07:25 PM PDT 24
Finished Mar 10 01:07:29 PM PDT 24
Peak memory 214552 kb
Host smart-7cee51b1-ea4a-4136-aac0-4d6e7fe82ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654134893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.654134893
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2676281524
Short name T233
Test name
Test status
Simulation time 195023877 ps
CPU time 1.63 seconds
Started Mar 10 01:07:24 PM PDT 24
Finished Mar 10 01:07:26 PM PDT 24
Peak memory 206332 kb
Host smart-2b72518a-30b3-47f7-a9bb-e18a043bba07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676281524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2676281524
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.177973307
Short name T949
Test name
Test status
Simulation time 59107815 ps
CPU time 1.14 seconds
Started Mar 10 01:07:22 PM PDT 24
Finished Mar 10 01:07:23 PM PDT 24
Peak memory 214640 kb
Host smart-dfddc677-39d4-4804-95ec-72491705512f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177973307 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.177973307
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.145298619
Short name T202
Test name
Test status
Simulation time 14219546 ps
CPU time 0.93 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:25 PM PDT 24
Peak memory 206296 kb
Host smart-fd817694-a3ac-4117-aeaa-012796b4fea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145298619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.145298619
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2709183387
Short name T941
Test name
Test status
Simulation time 35851310 ps
CPU time 0.85 seconds
Started Mar 10 01:07:25 PM PDT 24
Finished Mar 10 01:07:26 PM PDT 24
Peak memory 206296 kb
Host smart-5cddaead-337c-4031-9d35-f5f0bf781ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709183387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2709183387
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2831479950
Short name T900
Test name
Test status
Simulation time 41693496 ps
CPU time 1.03 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:24 PM PDT 24
Peak memory 206344 kb
Host smart-6ffdb748-36dd-419c-9ed6-af9750a0fd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831479950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2831479950
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3319215558
Short name T844
Test name
Test status
Simulation time 47790375 ps
CPU time 3.05 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:26 PM PDT 24
Peak memory 214608 kb
Host smart-e43fbff8-da96-46f8-b8b7-40e26235df75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319215558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3319215558
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1927934647
Short name T910
Test name
Test status
Simulation time 53990269 ps
CPU time 1.7 seconds
Started Mar 10 01:07:23 PM PDT 24
Finished Mar 10 01:07:25 PM PDT 24
Peak memory 206344 kb
Host smart-9f1ad329-6ab8-4b6e-a187-8b0f1c2366b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927934647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1927934647
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.81475809
Short name T767
Test name
Test status
Simulation time 65177516 ps
CPU time 1.15 seconds
Started Mar 10 01:35:50 PM PDT 24
Finished Mar 10 01:35:51 PM PDT 24
Peak memory 214792 kb
Host smart-8008bab9-cac0-4d40-8de5-2c529a0521b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81475809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.81475809
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.985051744
Short name T586
Test name
Test status
Simulation time 23728049 ps
CPU time 1.1 seconds
Started Mar 10 01:35:58 PM PDT 24
Finished Mar 10 01:35:59 PM PDT 24
Peak memory 205800 kb
Host smart-2781299a-1007-4499-aa07-f8384ee31be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985051744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.985051744
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4284877485
Short name T179
Test name
Test status
Simulation time 11704148 ps
CPU time 0.91 seconds
Started Mar 10 01:35:54 PM PDT 24
Finished Mar 10 01:35:55 PM PDT 24
Peak memory 214972 kb
Host smart-cacbb688-cde2-469c-b116-b951dfe4f9d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284877485 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4284877485
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.857740640
Short name T759
Test name
Test status
Simulation time 34321500 ps
CPU time 1.01 seconds
Started Mar 10 01:35:54 PM PDT 24
Finished Mar 10 01:35:56 PM PDT 24
Peak memory 215412 kb
Host smart-75dd87b4-7cb7-4413-a1df-d3c069c30570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857740640 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.857740640
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.571418374
Short name T704
Test name
Test status
Simulation time 61578028 ps
CPU time 0.94 seconds
Started Mar 10 01:35:55 PM PDT 24
Finished Mar 10 01:35:56 PM PDT 24
Peak memory 217168 kb
Host smart-af043238-8968-4189-856a-23d59ac555d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571418374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.571418374
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2074288489
Short name T347
Test name
Test status
Simulation time 49119488 ps
CPU time 0.97 seconds
Started Mar 10 01:35:51 PM PDT 24
Finished Mar 10 01:35:52 PM PDT 24
Peak memory 215724 kb
Host smart-302e56be-0644-4db3-b60f-198d8c7ed69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074288489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2074288489
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.95081111
Short name T528
Test name
Test status
Simulation time 26542681 ps
CPU time 1.02 seconds
Started Mar 10 01:35:55 PM PDT 24
Finished Mar 10 01:35:56 PM PDT 24
Peak memory 223264 kb
Host smart-842e801e-fb91-4eb8-8aa9-a79e53162298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95081111 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.95081111
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3745701097
Short name T251
Test name
Test status
Simulation time 26194485 ps
CPU time 0.89 seconds
Started Mar 10 01:35:49 PM PDT 24
Finished Mar 10 01:35:50 PM PDT 24
Peak memory 206168 kb
Host smart-c607009a-6969-4e6a-9e9f-05b5a44d9141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745701097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3745701097
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1723338697
Short name T56
Test name
Test status
Simulation time 464029452 ps
CPU time 6.67 seconds
Started Mar 10 01:35:56 PM PDT 24
Finished Mar 10 01:36:03 PM PDT 24
Peak memory 234952 kb
Host smart-8c094ab9-3621-497a-87f6-e419d60c526c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723338697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1723338697
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3677145686
Short name T533
Test name
Test status
Simulation time 29439027 ps
CPU time 0.91 seconds
Started Mar 10 01:35:55 PM PDT 24
Finished Mar 10 01:35:56 PM PDT 24
Peak memory 214420 kb
Host smart-d7823191-3435-40d9-ae23-6af3f313fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677145686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3677145686
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.635943823
Short name T354
Test name
Test status
Simulation time 259462231 ps
CPU time 2.82 seconds
Started Mar 10 01:35:55 PM PDT 24
Finished Mar 10 01:35:58 PM PDT 24
Peak memory 214344 kb
Host smart-33d5455e-9401-4258-b8d9-c43c58681d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635943823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.635943823
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2800923456
Short name T601
Test name
Test status
Simulation time 69930538343 ps
CPU time 1484.93 seconds
Started Mar 10 01:35:50 PM PDT 24
Finished Mar 10 02:00:35 PM PDT 24
Peak memory 222692 kb
Host smart-90f67b68-db22-490d-8a07-aa64bace53b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800923456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2800923456
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2487204571
Short name T754
Test name
Test status
Simulation time 46235892 ps
CPU time 0.91 seconds
Started Mar 10 01:36:01 PM PDT 24
Finished Mar 10 01:36:02 PM PDT 24
Peak memory 205728 kb
Host smart-ec15e82b-88b8-417b-a875-57730f9f04eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487204571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2487204571
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2908048766
Short name T370
Test name
Test status
Simulation time 222374616 ps
CPU time 1.23 seconds
Started Mar 10 01:36:09 PM PDT 24
Finished Mar 10 01:36:11 PM PDT 24
Peak memory 215420 kb
Host smart-a2fb3a19-6a04-45c7-89c3-e59697a3da42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908048766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2908048766
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.4287043127
Short name T701
Test name
Test status
Simulation time 29633838 ps
CPU time 0.92 seconds
Started Mar 10 01:35:57 PM PDT 24
Finished Mar 10 01:35:58 PM PDT 24
Peak memory 217012 kb
Host smart-1160a445-ce81-4d16-ac25-0fb0b6bb4f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287043127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4287043127
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2100549622
Short name T552
Test name
Test status
Simulation time 42836249 ps
CPU time 1.51 seconds
Started Mar 10 01:35:57 PM PDT 24
Finished Mar 10 01:35:59 PM PDT 24
Peak memory 216732 kb
Host smart-77ad0850-edd9-443d-83d2-62cd0f2fb023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100549622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2100549622
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_smoke.4247899999
Short name T771
Test name
Test status
Simulation time 39846623 ps
CPU time 0.88 seconds
Started Mar 10 01:35:56 PM PDT 24
Finished Mar 10 01:35:57 PM PDT 24
Peak memory 214364 kb
Host smart-8469da9b-1c4c-4287-8e3d-e46ed1717bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247899999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4247899999
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.580348793
Short name T489
Test name
Test status
Simulation time 840502889 ps
CPU time 4.96 seconds
Started Mar 10 01:35:56 PM PDT 24
Finished Mar 10 01:36:01 PM PDT 24
Peak memory 214404 kb
Host smart-a0e396c2-759b-4816-a040-b902e9cd0c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580348793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.580348793
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2559038963
Short name T187
Test name
Test status
Simulation time 119596799125 ps
CPU time 1418.51 seconds
Started Mar 10 01:35:54 PM PDT 24
Finished Mar 10 01:59:33 PM PDT 24
Peak memory 221796 kb
Host smart-77c9a5e5-6f07-456d-b176-476017e803ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559038963 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2559038963
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3466083756
Short name T781
Test name
Test status
Simulation time 32568964 ps
CPU time 1.29 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:35 PM PDT 24
Peak memory 214756 kb
Host smart-8fecb5d4-012a-46d2-9780-10560f6f1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466083756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3466083756
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2507015838
Short name T449
Test name
Test status
Simulation time 154486079 ps
CPU time 0.99 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 205996 kb
Host smart-69f2b88e-6b73-49a2-ba14-3b1c61369930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507015838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2507015838
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3469305505
Short name T696
Test name
Test status
Simulation time 27628699 ps
CPU time 1.08 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 216812 kb
Host smart-bbe62b27-1120-419b-a640-088686447387
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469305505 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3469305505
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2162759271
Short name T61
Test name
Test status
Simulation time 18761137 ps
CPU time 1.03 seconds
Started Mar 10 01:36:35 PM PDT 24
Finished Mar 10 01:36:37 PM PDT 24
Peak memory 217236 kb
Host smart-f3427ef0-8bad-40ca-8b7d-369008d51c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162759271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2162759271
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1374435493
Short name T724
Test name
Test status
Simulation time 23341278 ps
CPU time 1.19 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 215740 kb
Host smart-5fccc112-fde3-4bcf-b108-3101ad372c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374435493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1374435493
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.690125679
Short name T454
Test name
Test status
Simulation time 26108577 ps
CPU time 1.06 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 222492 kb
Host smart-f5e2a46e-5698-4490-ab99-411e3a622f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690125679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.690125679
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.227990183
Short name T468
Test name
Test status
Simulation time 17554357 ps
CPU time 1.04 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 214412 kb
Host smart-af4ce470-a5e5-47bf-9607-71f8bd6c9299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227990183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.227990183
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3305846578
Short name T345
Test name
Test status
Simulation time 115632190 ps
CPU time 2.87 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 218540 kb
Host smart-e2f307a9-3e7f-4a49-98bb-d6e957bcd462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305846578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3305846578
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1473416117
Short name T478
Test name
Test status
Simulation time 114741212270 ps
CPU time 790.55 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 220884 kb
Host smart-ce89bbe4-5cb4-4e80-a366-6aa9e4d9bd37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473416117 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1473416117
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.4266244918
Short name T410
Test name
Test status
Simulation time 196963871 ps
CPU time 1 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 215560 kb
Host smart-29b99dcf-4310-436c-a4d6-c3339adc458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266244918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4266244918
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1672925236
Short name T570
Test name
Test status
Simulation time 41671974 ps
CPU time 1.65 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:34 PM PDT 24
Peak memory 216848 kb
Host smart-e65644fa-6ed5-4456-9f5e-d867f6a1df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672925236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1672925236
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.206971411
Short name T238
Test name
Test status
Simulation time 37711425 ps
CPU time 1.71 seconds
Started Mar 10 01:38:29 PM PDT 24
Finished Mar 10 01:38:32 PM PDT 24
Peak memory 217136 kb
Host smart-de84ea87-a4cd-40e1-97db-9d39885482bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206971411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.206971411
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.571881009
Short name T545
Test name
Test status
Simulation time 83203259 ps
CPU time 1.12 seconds
Started Mar 10 01:38:29 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 215712 kb
Host smart-6f6e9943-ac7e-4fec-9efe-522cda47c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571881009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.571881009
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2156523899
Short name T583
Test name
Test status
Simulation time 294126920 ps
CPU time 4.01 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 217092 kb
Host smart-fabe46b8-b070-426a-805d-6246092b845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156523899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2156523899
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.582123363
Short name T443
Test name
Test status
Simulation time 35457608 ps
CPU time 1.39 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 216980 kb
Host smart-79ba0a0b-6795-4854-b1aa-145b548b4d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582123363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.582123363
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1597038941
Short name T740
Test name
Test status
Simulation time 24621499 ps
CPU time 1.21 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 216944 kb
Host smart-19b6f80e-f3b0-4133-9ead-9f0a1c8c346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597038941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1597038941
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3186078702
Short name T383
Test name
Test status
Simulation time 128416323 ps
CPU time 1.49 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 217276 kb
Host smart-08204005-665e-4337-9511-5bf258bd95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186078702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3186078702
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3848765504
Short name T379
Test name
Test status
Simulation time 43490013 ps
CPU time 1.35 seconds
Started Mar 10 01:38:27 PM PDT 24
Finished Mar 10 01:38:29 PM PDT 24
Peak memory 216776 kb
Host smart-e703c25d-536f-4c86-8dad-fbefa233d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848765504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3848765504
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4224186267
Short name T735
Test name
Test status
Simulation time 22800497 ps
CPU time 1.19 seconds
Started Mar 10 01:36:41 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 214788 kb
Host smart-3cf3dfd3-0309-4098-bb40-59b29ae0ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224186267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4224186267
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.285678147
Short name T783
Test name
Test status
Simulation time 32413900 ps
CPU time 0.97 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 206120 kb
Host smart-10aaf889-66ac-413c-accf-0d97de72967d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285678147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.285678147
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3537290710
Short name T460
Test name
Test status
Simulation time 31757020 ps
CPU time 0.85 seconds
Started Mar 10 01:36:39 PM PDT 24
Finished Mar 10 01:36:40 PM PDT 24
Peak memory 214828 kb
Host smart-57c3fbfe-c8c6-4096-8cba-57d157e4312f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537290710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3537290710
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3558186884
Short name T8
Test name
Test status
Simulation time 34574826 ps
CPU time 0.93 seconds
Started Mar 10 01:36:42 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 218688 kb
Host smart-35a22e8a-f8f4-4d26-b9aa-3bb2612de818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558186884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3558186884
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.76875421
Short name T721
Test name
Test status
Simulation time 21688721 ps
CPU time 0.92 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 214772 kb
Host smart-10ea9da8-3a58-40b8-bbc7-0d83201169ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76875421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.76875421
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.442791371
Short name T59
Test name
Test status
Simulation time 26517256 ps
CPU time 0.92 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 214336 kb
Host smart-5bea3838-5a7e-4cc8-9c4c-fd4fc86fbfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442791371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.442791371
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2227926694
Short name T653
Test name
Test status
Simulation time 49897039 ps
CPU time 1.55 seconds
Started Mar 10 01:36:32 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 206228 kb
Host smart-921de03a-3890-42df-be3f-c637b29559d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227926694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2227926694
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2551019339
Short name T359
Test name
Test status
Simulation time 63299600247 ps
CPU time 402.03 seconds
Started Mar 10 01:36:38 PM PDT 24
Finished Mar 10 01:43:21 PM PDT 24
Peak memory 217104 kb
Host smart-12fecd4a-c29f-487a-8329-8b206c506c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551019339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2551019339
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1342911214
Short name T680
Test name
Test status
Simulation time 95910851 ps
CPU time 1.21 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:32 PM PDT 24
Peak memory 215564 kb
Host smart-b7a2518c-d075-4380-a1e0-6053917dc62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342911214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1342911214
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.4171706642
Short name T803
Test name
Test status
Simulation time 66687398 ps
CPU time 1.84 seconds
Started Mar 10 01:38:37 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 216988 kb
Host smart-9f5be785-a525-4803-9e68-c80f87c68ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171706642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4171706642
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2264205519
Short name T805
Test name
Test status
Simulation time 34920901 ps
CPU time 1.04 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 215544 kb
Host smart-03746982-bea3-4fd8-8b2f-a0201e1d1546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264205519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2264205519
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1567352747
Short name T799
Test name
Test status
Simulation time 30434725 ps
CPU time 1.06 seconds
Started Mar 10 01:38:35 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 216716 kb
Host smart-7ffeace7-4799-409f-a4c2-20c90653a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567352747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1567352747
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3293914206
Short name T355
Test name
Test status
Simulation time 54072477 ps
CPU time 1.7 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 216824 kb
Host smart-9a66d7cb-bd2c-4da0-b3be-466e7e397bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293914206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3293914206
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.788903533
Short name T588
Test name
Test status
Simulation time 304905926 ps
CPU time 1.22 seconds
Started Mar 10 01:38:34 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 215552 kb
Host smart-c168e27c-3d91-4b05-af61-6dca5368de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788903533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.788903533
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3015860625
Short name T407
Test name
Test status
Simulation time 45177777 ps
CPU time 1.63 seconds
Started Mar 10 01:38:34 PM PDT 24
Finished Mar 10 01:38:36 PM PDT 24
Peak memory 216864 kb
Host smart-9f555159-58c8-4760-847d-92e81d8bd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015860625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3015860625
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2757579076
Short name T236
Test name
Test status
Simulation time 49119553 ps
CPU time 1.47 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 215756 kb
Host smart-83a19806-6ebe-433e-b463-5c6fdabc4359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757579076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2757579076
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1731363511
Short name T294
Test name
Test status
Simulation time 259532309 ps
CPU time 3.88 seconds
Started Mar 10 01:38:32 PM PDT 24
Finished Mar 10 01:38:36 PM PDT 24
Peak memory 218532 kb
Host smart-769aadf1-d4a8-468c-9a5e-f8dc50522694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731363511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1731363511
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1441269772
Short name T485
Test name
Test status
Simulation time 52601865 ps
CPU time 1.56 seconds
Started Mar 10 01:38:32 PM PDT 24
Finished Mar 10 01:38:34 PM PDT 24
Peak memory 215848 kb
Host smart-db2f1516-26a8-459f-998d-8df7eb995f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441269772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1441269772
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2522792810
Short name T638
Test name
Test status
Simulation time 25460697 ps
CPU time 1.05 seconds
Started Mar 10 01:36:39 PM PDT 24
Finished Mar 10 01:36:40 PM PDT 24
Peak memory 206008 kb
Host smart-edff3ddd-940b-43c1-9b5f-ba5ecd084bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522792810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2522792810
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.543770269
Short name T161
Test name
Test status
Simulation time 32878431 ps
CPU time 0.86 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 214868 kb
Host smart-b6b72e96-f386-4809-9938-98befd75a20b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543770269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.543770269
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2621065115
Short name T33
Test name
Test status
Simulation time 42582957 ps
CPU time 1.51 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:41 PM PDT 24
Peak memory 215412 kb
Host smart-f1c8ffdc-f7ea-4fe4-9497-c480043fd47b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621065115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2621065115
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3085788858
Short name T49
Test name
Test status
Simulation time 26139062 ps
CPU time 1.16 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 228964 kb
Host smart-71fd2796-3122-4e73-8a11-b573fb6d5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085788858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3085788858
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.342262456
Short name T736
Test name
Test status
Simulation time 41200599 ps
CPU time 1.48 seconds
Started Mar 10 01:36:39 PM PDT 24
Finished Mar 10 01:36:41 PM PDT 24
Peak memory 216852 kb
Host smart-a3f35fec-b822-4367-9788-2510d8e2ffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342262456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.342262456
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.1215372097
Short name T384
Test name
Test status
Simulation time 29344483 ps
CPU time 1.01 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 214440 kb
Host smart-288015fe-8a15-46a7-bed0-1c1c05f4ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215372097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1215372097
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1714370821
Short name T550
Test name
Test status
Simulation time 905206289 ps
CPU time 4.93 seconds
Started Mar 10 01:36:41 PM PDT 24
Finished Mar 10 01:36:48 PM PDT 24
Peak memory 215604 kb
Host smart-b592bc45-5509-4bff-badf-bb4699bf6532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714370821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1714370821
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3314171844
Short name T822
Test name
Test status
Simulation time 70287605411 ps
CPU time 830.73 seconds
Started Mar 10 01:36:38 PM PDT 24
Finished Mar 10 01:50:30 PM PDT 24
Peak memory 220840 kb
Host smart-9e3cf00f-a9c7-4e2a-ac2c-a1c8884099a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314171844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3314171844
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3188364066
Short name T331
Test name
Test status
Simulation time 60069023 ps
CPU time 1.24 seconds
Started Mar 10 01:38:36 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 216800 kb
Host smart-a1149435-6752-4fc8-b2d5-18b3cb07f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188364066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3188364066
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.120676071
Short name T426
Test name
Test status
Simulation time 72593438 ps
CPU time 3.06 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:36 PM PDT 24
Peak memory 217056 kb
Host smart-4f23ed5b-3887-47c2-b9a5-6d585ceb16d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120676071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.120676071
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3250464826
Short name T467
Test name
Test status
Simulation time 49140600 ps
CPU time 1.03 seconds
Started Mar 10 01:38:34 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 215548 kb
Host smart-21912150-946e-41aa-86b0-4293ab164547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250464826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3250464826
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3433083500
Short name T757
Test name
Test status
Simulation time 58032687 ps
CPU time 1.48 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 216864 kb
Host smart-eeb8d4b3-08dd-4c69-9c00-72a662d3324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433083500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3433083500
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1626589706
Short name T491
Test name
Test status
Simulation time 165884767 ps
CPU time 1.36 seconds
Started Mar 10 01:38:36 PM PDT 24
Finished Mar 10 01:38:38 PM PDT 24
Peak memory 217072 kb
Host smart-90c5a149-06f0-4660-9667-d04c23adeaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626589706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1626589706
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.4019678133
Short name T548
Test name
Test status
Simulation time 58508662 ps
CPU time 1.36 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 217040 kb
Host smart-ae6087d0-c0ed-4977-858c-0dc841fe9967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019678133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4019678133
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.4178359636
Short name T246
Test name
Test status
Simulation time 83529085 ps
CPU time 3 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:36 PM PDT 24
Peak memory 217148 kb
Host smart-c9d4d23f-14c8-4d0a-8898-20c4ee141f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178359636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4178359636
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.383192535
Short name T351
Test name
Test status
Simulation time 138292135 ps
CPU time 2.73 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:36 PM PDT 24
Peak memory 217124 kb
Host smart-05e16d95-bbce-4b1f-ae76-450c2b29ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383192535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.383192535
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2869170537
Short name T480
Test name
Test status
Simulation time 101848037 ps
CPU time 1.05 seconds
Started Mar 10 01:38:32 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 215780 kb
Host smart-5dfbf872-b61b-4f1b-8baf-191c905a1c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869170537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2869170537
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3031379133
Short name T220
Test name
Test status
Simulation time 153084960 ps
CPU time 1.16 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 214812 kb
Host smart-26178a66-0cd0-4dbe-b399-a110434f9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031379133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3031379133
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2343928895
Short name T343
Test name
Test status
Simulation time 12175101 ps
CPU time 0.86 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 204996 kb
Host smart-da3ec8f8-8616-49d5-9abf-bb095c5c80c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343928895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2343928895
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2561315445
Short name T516
Test name
Test status
Simulation time 42163252 ps
CPU time 0.85 seconds
Started Mar 10 01:36:48 PM PDT 24
Finished Mar 10 01:36:49 PM PDT 24
Peak memory 215016 kb
Host smart-609b3750-d7ac-4ded-8a3c-dccf67bdb5c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561315445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2561315445
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.923709246
Short name T534
Test name
Test status
Simulation time 66197954 ps
CPU time 1.16 seconds
Started Mar 10 01:36:45 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 215420 kb
Host smart-40a4e2b6-8b90-4497-840b-2160e33334d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923709246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.923709246
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2765340952
Short name T824
Test name
Test status
Simulation time 25905134 ps
CPU time 1.17 seconds
Started Mar 10 01:36:47 PM PDT 24
Finished Mar 10 01:36:48 PM PDT 24
Peak memory 216016 kb
Host smart-fcfa5ffa-2fb6-4c9e-9f64-18b31d39e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765340952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2765340952
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4224493845
Short name T235
Test name
Test status
Simulation time 54512649 ps
CPU time 1.55 seconds
Started Mar 10 01:36:45 PM PDT 24
Finished Mar 10 01:36:47 PM PDT 24
Peak memory 216892 kb
Host smart-396e77c1-1260-4d25-ac6d-523496fb84f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224493845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4224493845
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1542546138
Short name T134
Test name
Test status
Simulation time 40194372 ps
CPU time 0.83 seconds
Started Mar 10 01:36:47 PM PDT 24
Finished Mar 10 01:36:48 PM PDT 24
Peak memory 214680 kb
Host smart-2d6fd5d6-980f-4d72-b2b2-9c1d9bd75a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542546138 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1542546138
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1732412842
Short name T348
Test name
Test status
Simulation time 20557973 ps
CPU time 0.89 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 214396 kb
Host smart-ad5d9a45-e7b1-4719-8675-dcd80c8dced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732412842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1732412842
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4100181780
Short name T541
Test name
Test status
Simulation time 154704046 ps
CPU time 2.06 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:51 PM PDT 24
Peak memory 217736 kb
Host smart-5296d1da-93f0-43fa-8d7f-2185bc674716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100181780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4100181780
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.2870203984
Short name T606
Test name
Test status
Simulation time 48742095 ps
CPU time 1.37 seconds
Started Mar 10 01:38:33 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 217056 kb
Host smart-285bdef7-90fc-4be6-b0c4-f8e5b2fb66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870203984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2870203984
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2405446817
Short name T838
Test name
Test status
Simulation time 82024464 ps
CPU time 1.33 seconds
Started Mar 10 01:38:34 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 216944 kb
Host smart-cea2a1e5-b554-4207-995b-a30411a18604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405446817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2405446817
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3587520705
Short name T360
Test name
Test status
Simulation time 90492852 ps
CPU time 1.18 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 215648 kb
Host smart-aa0c2a0a-c0bf-4251-bf74-0287ea231edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587520705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3587520705
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.973992908
Short name T488
Test name
Test status
Simulation time 35829735 ps
CPU time 1.49 seconds
Started Mar 10 01:38:39 PM PDT 24
Finished Mar 10 01:38:41 PM PDT 24
Peak memory 216972 kb
Host smart-e14f0906-e750-47d3-8860-e4c6fbf2dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973992908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.973992908
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2267450327
Short name T659
Test name
Test status
Simulation time 134643968 ps
CPU time 1.22 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:39 PM PDT 24
Peak memory 214496 kb
Host smart-ac910a62-ad67-4f39-a957-70cfd4061adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267450327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2267450327
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2178090708
Short name T690
Test name
Test status
Simulation time 37461442 ps
CPU time 1.38 seconds
Started Mar 10 01:38:35 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 215600 kb
Host smart-78793590-0ccf-4382-aac8-0220ad222596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178090708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2178090708
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2904500060
Short name T507
Test name
Test status
Simulation time 38286700 ps
CPU time 1.59 seconds
Started Mar 10 01:38:37 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 215828 kb
Host smart-0ba37ee1-b981-4d59-8950-f9528a5c5548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904500060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2904500060
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3930660795
Short name T334
Test name
Test status
Simulation time 26327462 ps
CPU time 1.25 seconds
Started Mar 10 01:38:39 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 218092 kb
Host smart-03f04b31-88cf-4e81-b27c-0baffe096300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930660795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3930660795
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.465217721
Short name T635
Test name
Test status
Simulation time 14894303 ps
CPU time 0.95 seconds
Started Mar 10 01:36:45 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 206136 kb
Host smart-202d27a9-3543-4855-b917-6d82728fba87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465217721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.465217721
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2662952610
Short name T114
Test name
Test status
Simulation time 20476957 ps
CPU time 0.91 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 215032 kb
Host smart-8a48f2a7-434c-4969-adec-00c013056e63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662952610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2662952610
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2801790969
Short name T45
Test name
Test status
Simulation time 19678787 ps
CPU time 1.11 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:46 PM PDT 24
Peak memory 222336 kb
Host smart-47789c62-dcc2-4947-b616-b32cb55fc57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801790969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2801790969
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3664984381
Short name T482
Test name
Test status
Simulation time 40812743 ps
CPU time 1.11 seconds
Started Mar 10 01:36:44 PM PDT 24
Finished Mar 10 01:36:45 PM PDT 24
Peak memory 215544 kb
Host smart-6fd7de80-4b5a-417f-9202-9a25dc1ac96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664984381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3664984381
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2928095930
Short name T708
Test name
Test status
Simulation time 24966240 ps
CPU time 0.91 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 214768 kb
Host smart-ccd90629-8945-48b4-9af4-aa16060f1fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928095930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2928095930
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2782917404
Short name T402
Test name
Test status
Simulation time 15031343 ps
CPU time 0.92 seconds
Started Mar 10 01:36:48 PM PDT 24
Finished Mar 10 01:36:49 PM PDT 24
Peak memory 214384 kb
Host smart-d252ed4a-e024-4103-a31f-13c26db55e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782917404 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2782917404
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2891654835
Short name T476
Test name
Test status
Simulation time 146759615 ps
CPU time 2.16 seconds
Started Mar 10 01:36:47 PM PDT 24
Finished Mar 10 01:36:49 PM PDT 24
Peak memory 215392 kb
Host smart-5d53f70f-b4b0-415f-bf12-28d20cda6afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891654835 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2891654835
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4250342143
Short name T512
Test name
Test status
Simulation time 46364101762 ps
CPU time 1136.86 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:55:40 PM PDT 24
Peak memory 217856 kb
Host smart-0f8b04a9-1628-4496-901c-96575d843732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250342143 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4250342143
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.896508623
Short name T39
Test name
Test status
Simulation time 36931649 ps
CPU time 1.62 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:41 PM PDT 24
Peak memory 215808 kb
Host smart-36d7d40c-2c97-4a9d-bb21-c9750d9566d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896508623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.896508623
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1429488241
Short name T273
Test name
Test status
Simulation time 56728320 ps
CPU time 1.52 seconds
Started Mar 10 01:38:39 PM PDT 24
Finished Mar 10 01:38:41 PM PDT 24
Peak memory 215904 kb
Host smart-0dc74e55-0201-4474-a6a8-5ab7bbb8b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429488241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1429488241
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1518309111
Short name T326
Test name
Test status
Simulation time 60943351 ps
CPU time 1.53 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 216868 kb
Host smart-ad767fef-0e9a-4294-a6ff-8ece283c30f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518309111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1518309111
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3996959248
Short name T237
Test name
Test status
Simulation time 90707706 ps
CPU time 1.13 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:39 PM PDT 24
Peak memory 215712 kb
Host smart-d207e6ce-829d-446d-a7f1-a1a4de2a41fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996959248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3996959248
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.615256106
Short name T751
Test name
Test status
Simulation time 202898893 ps
CPU time 1.22 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 215884 kb
Host smart-357c649b-2506-441d-b651-fbe3f66bf74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615256106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.615256106
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3741686312
Short name T578
Test name
Test status
Simulation time 25303656 ps
CPU time 1.26 seconds
Started Mar 10 01:38:40 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216776 kb
Host smart-4c812b01-704e-42de-b105-11c3c0183f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741686312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3741686312
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2307799963
Short name T304
Test name
Test status
Simulation time 240207661 ps
CPU time 1.13 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 215680 kb
Host smart-814d8380-5946-4700-8a3d-dd13e7071222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307799963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2307799963
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3572710503
Short name T293
Test name
Test status
Simulation time 56846737 ps
CPU time 1.04 seconds
Started Mar 10 01:38:39 PM PDT 24
Finished Mar 10 01:38:41 PM PDT 24
Peak memory 217040 kb
Host smart-131170fb-99ba-422b-9044-9e375d91c784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572710503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3572710503
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1036127152
Short name T389
Test name
Test status
Simulation time 37309362 ps
CPU time 1.23 seconds
Started Mar 10 01:38:37 PM PDT 24
Finished Mar 10 01:38:38 PM PDT 24
Peak memory 215640 kb
Host smart-89319afc-0b6f-4f6e-86ea-0bf88b106aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036127152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1036127152
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.161188840
Short name T63
Test name
Test status
Simulation time 70899058 ps
CPU time 1.14 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 214744 kb
Host smart-493c9a4b-5706-4276-b3fe-407efcba7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161188840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.161188840
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1450381119
Short name T782
Test name
Test status
Simulation time 47797424 ps
CPU time 0.91 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 206120 kb
Host smart-9327b77e-0cfa-4c64-ac90-1227fcca96c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450381119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1450381119
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1809400588
Short name T709
Test name
Test status
Simulation time 33650713 ps
CPU time 0.87 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:36:54 PM PDT 24
Peak memory 214960 kb
Host smart-57a657a4-fd89-4b6e-9059-aa01e44818f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809400588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1809400588
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1884494258
Short name T356
Test name
Test status
Simulation time 215460443 ps
CPU time 1.01 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:52 PM PDT 24
Peak memory 215608 kb
Host smart-f4af9c57-4224-4cec-b9e3-a9194492cba1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884494258 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1884494258
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1840030501
Short name T310
Test name
Test status
Simulation time 18650698 ps
CPU time 1 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:36:55 PM PDT 24
Peak memory 217012 kb
Host smart-ff23830c-9540-4545-84db-234f3337d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840030501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1840030501
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.649357312
Short name T706
Test name
Test status
Simulation time 95998681 ps
CPU time 1.41 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:52 PM PDT 24
Peak memory 215700 kb
Host smart-fcc74247-1afd-4f55-b703-bfaa5f0d4e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649357312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.649357312
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.2623230199
Short name T399
Test name
Test status
Simulation time 24035956 ps
CPU time 0.94 seconds
Started Mar 10 01:36:43 PM PDT 24
Finished Mar 10 01:36:44 PM PDT 24
Peak memory 214460 kb
Host smart-5896a17f-979b-4901-a972-38e8cddd35c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623230199 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2623230199
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2726439471
Short name T424
Test name
Test status
Simulation time 199520852 ps
CPU time 2.57 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:53 PM PDT 24
Peak memory 218588 kb
Host smart-723cf1c8-f71b-408b-864c-203b3f37b2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726439471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2726439471
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3589906295
Short name T419
Test name
Test status
Simulation time 96480419065 ps
CPU time 607.2 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:47:01 PM PDT 24
Peak memory 218820 kb
Host smart-42ca3864-fef2-4f01-85e7-1c3351dae998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589906295 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3589906295
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.edn_genbits.1949300372
Short name T365
Test name
Test status
Simulation time 51533304 ps
CPU time 1.96 seconds
Started Mar 10 01:38:37 PM PDT 24
Finished Mar 10 01:38:40 PM PDT 24
Peak memory 216672 kb
Host smart-fc894a1e-c26f-4f18-9f14-39bb08605983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949300372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1949300372
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1483501760
Short name T357
Test name
Test status
Simulation time 61376520 ps
CPU time 1.29 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216876 kb
Host smart-4a1021fe-474f-4ef9-83e9-15358d184ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483501760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1483501760
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3600624609
Short name T278
Test name
Test status
Simulation time 37727630 ps
CPU time 1.25 seconds
Started Mar 10 01:38:38 PM PDT 24
Finished Mar 10 01:38:39 PM PDT 24
Peak memory 216840 kb
Host smart-5b7d02b2-88c7-4dc5-90e4-9bd9a7ef2a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600624609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3600624609
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2563732825
Short name T600
Test name
Test status
Simulation time 100156534 ps
CPU time 1.45 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 217176 kb
Host smart-0cef2401-c216-44d8-a5d2-1f5f05d5ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563732825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2563732825
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.4137064395
Short name T763
Test name
Test status
Simulation time 42839093 ps
CPU time 1.27 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 215752 kb
Host smart-29623d5b-5dee-4471-9e35-d171e2f0a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137064395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4137064395
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3500802879
Short name T41
Test name
Test status
Simulation time 50174564 ps
CPU time 1.79 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:50 PM PDT 24
Peak memory 215848 kb
Host smart-4b19d990-5278-49b9-a863-c1471e143862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500802879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3500802879
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4194315873
Short name T292
Test name
Test status
Simulation time 96153778 ps
CPU time 1.28 seconds
Started Mar 10 01:38:44 PM PDT 24
Finished Mar 10 01:38:46 PM PDT 24
Peak memory 218304 kb
Host smart-f1cc2aa7-f74a-4458-9ee7-5e2f2d0b5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194315873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4194315873
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.76653305
Short name T692
Test name
Test status
Simulation time 42837508 ps
CPU time 1.14 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:36:55 PM PDT 24
Peak memory 214792 kb
Host smart-dc9750dc-7ca8-49fc-93e4-4b57b13ab0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76653305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.76653305
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2487843461
Short name T453
Test name
Test status
Simulation time 64206957 ps
CPU time 0.87 seconds
Started Mar 10 01:36:59 PM PDT 24
Finished Mar 10 01:37:00 PM PDT 24
Peak memory 204656 kb
Host smart-54925d97-1142-43c2-9c1a-7f052bdf183d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487843461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2487843461
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.844319198
Short name T643
Test name
Test status
Simulation time 12607623 ps
CPU time 0.93 seconds
Started Mar 10 01:36:51 PM PDT 24
Finished Mar 10 01:36:52 PM PDT 24
Peak memory 214892 kb
Host smart-2bf5ef9b-6adc-40f6-a8e1-833c4f3382b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844319198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.844319198
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2992142606
Short name T584
Test name
Test status
Simulation time 109404610 ps
CPU time 1.11 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 216800 kb
Host smart-4071ba54-4142-4cae-9880-2aeddcba9b37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992142606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2992142606
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2442989020
Short name T431
Test name
Test status
Simulation time 39002774 ps
CPU time 0.83 seconds
Started Mar 10 01:36:48 PM PDT 24
Finished Mar 10 01:36:49 PM PDT 24
Peak memory 217136 kb
Host smart-b1df460f-8b6d-4004-b909-15ef7ac393a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442989020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2442989020
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.604377764
Short name T182
Test name
Test status
Simulation time 109562462 ps
CPU time 1.12 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 217040 kb
Host smart-74723dd9-d8cf-4b86-bd55-63342561611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604377764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.604377764
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4209318135
Short name T546
Test name
Test status
Simulation time 35171768 ps
CPU time 0.87 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:51 PM PDT 24
Peak memory 214644 kb
Host smart-e6a41dc9-3216-42bd-bfeb-2e4d45dcff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209318135 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4209318135
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3863639
Short name T145
Test name
Test status
Simulation time 25332317 ps
CPU time 0.96 seconds
Started Mar 10 01:36:50 PM PDT 24
Finished Mar 10 01:36:52 PM PDT 24
Peak memory 214380 kb
Host smart-22618fb0-a23a-410d-9c67-04ba4a298de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863639 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3863639
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1753293017
Short name T385
Test name
Test status
Simulation time 705142918 ps
CPU time 4.27 seconds
Started Mar 10 01:36:49 PM PDT 24
Finished Mar 10 01:36:53 PM PDT 24
Peak memory 215648 kb
Host smart-224bfdf4-450f-40ae-8259-1ade3c3b0935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753293017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1753293017
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3221046743
Short name T267
Test name
Test status
Simulation time 108261104563 ps
CPU time 1198.39 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:56:52 PM PDT 24
Peak memory 223300 kb
Host smart-a724a757-7c30-4345-9ed5-c6246ab562b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221046743 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3221046743
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2567891518
Short name T756
Test name
Test status
Simulation time 74749130 ps
CPU time 1.29 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 215724 kb
Host smart-d6f97a8c-78d5-43bb-b2a2-80ed0db04321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567891518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2567891518
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3060725749
Short name T1
Test name
Test status
Simulation time 84948610 ps
CPU time 1.14 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216792 kb
Host smart-79ad6d13-0f41-4cf5-9a28-3a8662f39965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060725749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3060725749
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.4163102441
Short name T800
Test name
Test status
Simulation time 75735632 ps
CPU time 2.72 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:46 PM PDT 24
Peak memory 217044 kb
Host smart-12ec449e-9fc6-41d9-b971-7e287e945855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163102441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4163102441
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.4173967262
Short name T831
Test name
Test status
Simulation time 44099469 ps
CPU time 1.86 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216916 kb
Host smart-f667bb01-f617-43b4-9dfd-ea4d4cfe4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173967262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.4173967262
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1337879537
Short name T538
Test name
Test status
Simulation time 82557927 ps
CPU time 1.18 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:44 PM PDT 24
Peak memory 218796 kb
Host smart-5ed90cb2-08ed-40e3-b45f-2b8f2861b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337879537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1337879537
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3461741275
Short name T362
Test name
Test status
Simulation time 292831437 ps
CPU time 2.5 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:50 PM PDT 24
Peak memory 217976 kb
Host smart-3e507054-f03f-4ee0-8a17-30b009987612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461741275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3461741275
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2791464870
Short name T24
Test name
Test status
Simulation time 120911371 ps
CPU time 1.75 seconds
Started Mar 10 01:38:40 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216988 kb
Host smart-a368306c-83f9-4625-ad86-c4adff601a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791464870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2791464870
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2359917534
Short name T412
Test name
Test status
Simulation time 115061031 ps
CPU time 2.48 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:48 PM PDT 24
Peak memory 218348 kb
Host smart-a67f8355-a8b9-4346-87c2-3451b6a39a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359917534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2359917534
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2657946044
Short name T559
Test name
Test status
Simulation time 33107717 ps
CPU time 1.6 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:45 PM PDT 24
Peak memory 216848 kb
Host smart-1b0007b0-64be-4b1e-a6fc-bd45184869ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657946044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2657946044
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1595950385
Short name T589
Test name
Test status
Simulation time 39135907 ps
CPU time 1.14 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:45 PM PDT 24
Peak memory 216064 kb
Host smart-80c98dca-4edd-4f03-8f51-659c518538c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595950385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1595950385
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1160877285
Short name T312
Test name
Test status
Simulation time 81919808 ps
CPU time 1.23 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:37:00 PM PDT 24
Peak memory 215504 kb
Host smart-b6b1bcf2-9be8-4b64-a960-f519f04e4676
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160877285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1160877285
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.617737950
Short name T91
Test name
Test status
Simulation time 20996076 ps
CPU time 1.13 seconds
Started Mar 10 01:36:55 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 230532 kb
Host smart-e86cbbaf-dad6-4190-91ac-721f43faff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617737950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.617737950
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.2495334818
Short name T337
Test name
Test status
Simulation time 22694142 ps
CPU time 1.1 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 214712 kb
Host smart-f961bcba-7205-4b58-a156-b32fada27c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495334818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2495334818
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.133867593
Short name T141
Test name
Test status
Simulation time 31371014 ps
CPU time 0.98 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 214396 kb
Host smart-8d58098f-085f-4d7d-aebe-e6dbc78fb44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133867593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.133867593
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3329545099
Short name T532
Test name
Test status
Simulation time 810153103 ps
CPU time 4.44 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 214404 kb
Host smart-9ed84f1f-2941-4e83-b88b-7800609c2233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329545099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3329545099
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3435690299
Short name T504
Test name
Test status
Simulation time 17476030646 ps
CPU time 451.71 seconds
Started Mar 10 01:36:53 PM PDT 24
Finished Mar 10 01:44:25 PM PDT 24
Peak memory 216928 kb
Host smart-3f614eac-d321-494f-aa44-3c7e4d03ffd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435690299 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3435690299
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3711919454
Short name T176
Test name
Test status
Simulation time 70544186 ps
CPU time 1.49 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 217120 kb
Host smart-8baf7f25-802f-4326-bb93-400fb7762a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711919454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3711919454
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.4046346048
Short name T325
Test name
Test status
Simulation time 41038917 ps
CPU time 1.1 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 215624 kb
Host smart-14fdcbba-8f9c-4a12-b8ae-c4128bec897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046346048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4046346048
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2958725408
Short name T413
Test name
Test status
Simulation time 68790369 ps
CPU time 1.48 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:44 PM PDT 24
Peak memory 218364 kb
Host smart-bf934cf6-b77d-45f9-b4d1-daca407dc167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958725408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2958725408
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2945644805
Short name T723
Test name
Test status
Simulation time 119077154 ps
CPU time 1.35 seconds
Started Mar 10 01:38:42 PM PDT 24
Finished Mar 10 01:38:44 PM PDT 24
Peak memory 215872 kb
Host smart-8f421c87-606d-4fb2-9905-4ef856d62294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945644805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2945644805
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2330557251
Short name T604
Test name
Test status
Simulation time 43984117 ps
CPU time 1.46 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 217956 kb
Host smart-1ea93183-0cdb-4b4d-9989-3cd8be41426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330557251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2330557251
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.435039347
Short name T580
Test name
Test status
Simulation time 30265663 ps
CPU time 1.18 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:44 PM PDT 24
Peak memory 215480 kb
Host smart-25d2f234-bbe9-4aed-aea6-2f9b1338179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435039347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.435039347
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2502803352
Short name T563
Test name
Test status
Simulation time 40392932 ps
CPU time 1.37 seconds
Started Mar 10 01:38:43 PM PDT 24
Finished Mar 10 01:38:45 PM PDT 24
Peak memory 215680 kb
Host smart-835bf099-c628-44ee-85eb-b442a85185b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502803352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2502803352
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1914434008
Short name T520
Test name
Test status
Simulation time 75426294 ps
CPU time 1.22 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 216848 kb
Host smart-d90d09a0-434a-4fa4-af2f-377ca2efc9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914434008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1914434008
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1763241053
Short name T341
Test name
Test status
Simulation time 78329109 ps
CPU time 1.16 seconds
Started Mar 10 01:38:45 PM PDT 24
Finished Mar 10 01:38:47 PM PDT 24
Peak memory 215788 kb
Host smart-ecbd090e-9f0a-4757-8c06-067e9001546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763241053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1763241053
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.594162074
Short name T148
Test name
Test status
Simulation time 86490380 ps
CPU time 1.11 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:37:00 PM PDT 24
Peak memory 214816 kb
Host smart-e7b32c12-8438-4b04-95d7-96143ac3cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594162074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.594162074
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.394667929
Short name T542
Test name
Test status
Simulation time 14580057 ps
CPU time 0.95 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 206092 kb
Host smart-7fd27c27-9d9c-47c7-ad91-d20dddb59074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394667929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.394667929
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1187245300
Short name T697
Test name
Test status
Simulation time 152779426 ps
CPU time 1.02 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 216872 kb
Host smart-dff1a430-aa05-4400-a177-3cf07999dc7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187245300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1187245300
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.1796445523
Short name T765
Test name
Test status
Simulation time 75821395 ps
CPU time 1.43 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 216892 kb
Host smart-76b3665f-ee30-41d1-a2e4-54f2aa5d1097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796445523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1796445523
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2212339162
Short name T575
Test name
Test status
Simulation time 35279855 ps
CPU time 0.87 seconds
Started Mar 10 01:36:57 PM PDT 24
Finished Mar 10 01:36:59 PM PDT 24
Peak memory 214680 kb
Host smart-8ddcdf22-dafb-480a-be0c-3fc784fd6162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212339162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2212339162
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2318071586
Short name T336
Test name
Test status
Simulation time 49739277 ps
CPU time 0.94 seconds
Started Mar 10 01:36:54 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 214424 kb
Host smart-94504e10-7bfe-43b4-9e26-fb054a746923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318071586 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2318071586
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1308141707
Short name T830
Test name
Test status
Simulation time 385920184 ps
CPU time 2.2 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:58 PM PDT 24
Peak memory 217948 kb
Host smart-97bdfeb0-d1b9-4f50-923a-9a5ce3b399df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308141707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1308141707
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1008226819
Short name T766
Test name
Test status
Simulation time 315250331234 ps
CPU time 564.23 seconds
Started Mar 10 01:36:55 PM PDT 24
Finished Mar 10 01:46:20 PM PDT 24
Peak memory 217336 kb
Host smart-50185179-d613-4783-b0b7-eb0885f32022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008226819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1008226819
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2935158163
Short name T725
Test name
Test status
Simulation time 50493868 ps
CPU time 1.84 seconds
Started Mar 10 01:38:41 PM PDT 24
Finished Mar 10 01:38:43 PM PDT 24
Peak memory 216824 kb
Host smart-17f49306-b1e7-4fcf-99d5-6d3c3fd91365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935158163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2935158163
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3344350070
Short name T826
Test name
Test status
Simulation time 39828698 ps
CPU time 1.55 seconds
Started Mar 10 01:38:49 PM PDT 24
Finished Mar 10 01:38:51 PM PDT 24
Peak memory 214416 kb
Host smart-59284358-deaf-4b9b-a16e-94572ae7c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344350070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3344350070
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1530909359
Short name T349
Test name
Test status
Simulation time 39986050 ps
CPU time 1.62 seconds
Started Mar 10 01:38:50 PM PDT 24
Finished Mar 10 01:38:52 PM PDT 24
Peak memory 216800 kb
Host smart-a382bd73-8348-4b8f-ba00-98281fb8a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530909359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1530909359
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1607676584
Short name T461
Test name
Test status
Simulation time 102594668 ps
CPU time 1.08 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 215700 kb
Host smart-f5cf9912-9446-4139-a9f0-42574e1c9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607676584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1607676584
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1381452987
Short name T7
Test name
Test status
Simulation time 139807396 ps
CPU time 1.72 seconds
Started Mar 10 01:38:48 PM PDT 24
Finished Mar 10 01:38:50 PM PDT 24
Peak memory 217176 kb
Host smart-74a0bab2-d377-46a6-ab05-f746e1a2d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381452987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1381452987
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2820430912
Short name T178
Test name
Test status
Simulation time 165114645 ps
CPU time 0.99 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:52 PM PDT 24
Peak memory 215608 kb
Host smart-3422c8b8-1f76-4c12-a612-4e78fec5410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820430912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2820430912
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.694519373
Short name T785
Test name
Test status
Simulation time 88038774 ps
CPU time 1.24 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:48 PM PDT 24
Peak memory 217084 kb
Host smart-9e1ca54e-ca10-4960-9671-96ea78e87441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694519373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.694519373
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1924762222
Short name T710
Test name
Test status
Simulation time 54396137 ps
CPU time 1.29 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 216968 kb
Host smart-0bfd6d80-d3db-491d-bf0a-803383a54e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924762222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1924762222
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.1627018029
Short name T602
Test name
Test status
Simulation time 32252453 ps
CPU time 1.1 seconds
Started Mar 10 01:37:01 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 205384 kb
Host smart-5c4a9233-a406-4aa8-9bf4-613be34c6739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627018029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1627018029
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1141135995
Short name T511
Test name
Test status
Simulation time 27297257 ps
CPU time 0.84 seconds
Started Mar 10 01:37:01 PM PDT 24
Finished Mar 10 01:37:04 PM PDT 24
Peak memory 214864 kb
Host smart-cbe86f3d-8d2f-4da9-80a3-c63240b87be5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141135995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1141135995
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3594851649
Short name T558
Test name
Test status
Simulation time 46076374 ps
CPU time 1.08 seconds
Started Mar 10 01:37:01 PM PDT 24
Finished Mar 10 01:37:04 PM PDT 24
Peak memory 216720 kb
Host smart-64242621-c621-44f2-a866-b8a984604745
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594851649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3594851649
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.4149604665
Short name T47
Test name
Test status
Simulation time 93734597 ps
CPU time 0.99 seconds
Started Mar 10 01:37:02 PM PDT 24
Finished Mar 10 01:37:04 PM PDT 24
Peak memory 222156 kb
Host smart-61e3e4c6-7efb-4881-9238-24fde4598e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149604665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4149604665
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1438244474
Short name T628
Test name
Test status
Simulation time 101051930 ps
CPU time 1.34 seconds
Started Mar 10 01:36:59 PM PDT 24
Finished Mar 10 01:37:01 PM PDT 24
Peak memory 215484 kb
Host smart-4d0b5a93-cf1b-4065-b1d3-abaefb9e41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438244474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1438244474
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2263666025
Short name T132
Test name
Test status
Simulation time 23179751 ps
CPU time 0.97 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:08 PM PDT 24
Peak memory 214772 kb
Host smart-19a4e5d9-18fa-404e-bb80-35e653f18d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263666025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2263666025
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.991130095
Short name T505
Test name
Test status
Simulation time 14390320 ps
CPU time 0.94 seconds
Started Mar 10 01:36:56 PM PDT 24
Finished Mar 10 01:36:57 PM PDT 24
Peak memory 214396 kb
Host smart-32969413-51da-481a-aa32-764355aeec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991130095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.991130095
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/190.edn_genbits.3406676349
Short name T288
Test name
Test status
Simulation time 94614535 ps
CPU time 1.18 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 215580 kb
Host smart-743275b9-f8e6-4864-ae2f-31426b4496cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406676349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3406676349
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.808970502
Short name T392
Test name
Test status
Simulation time 53661479 ps
CPU time 1.29 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 217124 kb
Host smart-a1acd547-3580-4ef6-9f7f-c7ce5e86b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808970502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.808970502
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3543002622
Short name T12
Test name
Test status
Simulation time 45513603 ps
CPU time 1.54 seconds
Started Mar 10 01:38:46 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 214368 kb
Host smart-7b57e79e-6721-4bf9-a87c-cd11b11f8335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543002622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3543002622
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1826737514
Short name T185
Test name
Test status
Simulation time 92550792 ps
CPU time 1.16 seconds
Started Mar 10 01:38:48 PM PDT 24
Finished Mar 10 01:38:51 PM PDT 24
Peak memory 215708 kb
Host smart-fc471d05-4cde-4f95-9584-592b04aa6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826737514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1826737514
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1355521261
Short name T391
Test name
Test status
Simulation time 114449406 ps
CPU time 1.36 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 217264 kb
Host smart-75e48fa9-00fa-4478-a0f5-1b94fe366894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355521261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1355521261
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3024698049
Short name T285
Test name
Test status
Simulation time 41455873 ps
CPU time 1.24 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 217028 kb
Host smart-d89f6f08-df86-4c21-abc6-58169de45674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024698049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3024698049
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.555239236
Short name T753
Test name
Test status
Simulation time 42048543 ps
CPU time 1.7 seconds
Started Mar 10 01:38:48 PM PDT 24
Finished Mar 10 01:38:50 PM PDT 24
Peak memory 216920 kb
Host smart-bdb4d868-4a54-48a5-b5b7-2bc7e2c433eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555239236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.555239236
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4170530447
Short name T320
Test name
Test status
Simulation time 45878649 ps
CPU time 1.53 seconds
Started Mar 10 01:38:47 PM PDT 24
Finished Mar 10 01:38:49 PM PDT 24
Peak memory 216908 kb
Host smart-524506fe-0cf1-4516-9092-8af4c3eac5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170530447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4170530447
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3959838886
Short name T405
Test name
Test status
Simulation time 44432393 ps
CPU time 1.62 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 216996 kb
Host smart-70ca4a96-68b7-404b-a547-ab3a6805416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959838886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3959838886
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.990770957
Short name T582
Test name
Test status
Simulation time 100717259 ps
CPU time 1.34 seconds
Started Mar 10 01:38:49 PM PDT 24
Finished Mar 10 01:38:51 PM PDT 24
Peak memory 218312 kb
Host smart-a70067a8-db45-4290-a8c5-84c91d4a4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990770957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.990770957
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3745554991
Short name T714
Test name
Test status
Simulation time 34128715 ps
CPU time 1.4 seconds
Started Mar 10 01:36:02 PM PDT 24
Finished Mar 10 01:36:03 PM PDT 24
Peak memory 214816 kb
Host smart-a3189420-52a5-41c1-a959-a9918f80e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745554991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3745554991
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2290781624
Short name T668
Test name
Test status
Simulation time 30347819 ps
CPU time 0.99 seconds
Started Mar 10 01:36:06 PM PDT 24
Finished Mar 10 01:36:07 PM PDT 24
Peak memory 206108 kb
Host smart-010489f7-126f-456a-a529-70858119e582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290781624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2290781624
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.750154002
Short name T94
Test name
Test status
Simulation time 25382483 ps
CPU time 0.88 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:06 PM PDT 24
Peak memory 214908 kb
Host smart-f032875b-fac5-48c2-8c21-fe9ba145de26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750154002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.750154002
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.2097287504
Short name T415
Test name
Test status
Simulation time 19930970 ps
CPU time 0.95 seconds
Started Mar 10 01:36:04 PM PDT 24
Finished Mar 10 01:36:05 PM PDT 24
Peak memory 216840 kb
Host smart-77d90fd5-89fa-4219-b7f5-d0ca0e28e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097287504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2097287504
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3404201485
Short name T747
Test name
Test status
Simulation time 96001444 ps
CPU time 1.28 seconds
Started Mar 10 01:36:02 PM PDT 24
Finished Mar 10 01:36:03 PM PDT 24
Peak memory 215688 kb
Host smart-575d5cd1-c622-4998-b1ce-55288674c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404201485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3404201485
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3928365115
Short name T122
Test name
Test status
Simulation time 28667722 ps
CPU time 0.85 seconds
Started Mar 10 01:36:02 PM PDT 24
Finished Mar 10 01:36:03 PM PDT 24
Peak memory 214636 kb
Host smart-0bdfaeb4-1247-46dc-9c13-3464b335ecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928365115 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3928365115
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2450525948
Short name T55
Test name
Test status
Simulation time 3244901271 ps
CPU time 6.2 seconds
Started Mar 10 01:36:07 PM PDT 24
Finished Mar 10 01:36:13 PM PDT 24
Peak memory 236496 kb
Host smart-1447e416-dbc5-428a-a93e-3a73b752069c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450525948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2450525948
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3094063202
Short name T3
Test name
Test status
Simulation time 40000192 ps
CPU time 0.91 seconds
Started Mar 10 01:36:01 PM PDT 24
Finished Mar 10 01:36:02 PM PDT 24
Peak memory 214408 kb
Host smart-a05a67c2-ad6d-42e4-866b-78cc37d9ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094063202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3094063202
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1134266954
Short name T330
Test name
Test status
Simulation time 158793997 ps
CPU time 3.52 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:08 PM PDT 24
Peak memory 215516 kb
Host smart-34be80da-330e-4533-8187-50e751a5acdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134266954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1134266954
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2874532067
Short name T671
Test name
Test status
Simulation time 192775978075 ps
CPU time 798.07 seconds
Started Mar 10 01:36:02 PM PDT 24
Finished Mar 10 01:49:21 PM PDT 24
Peak memory 236272 kb
Host smart-5e84c6d3-c11d-4301-8efa-1d5f8b772db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874532067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2874532067
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.154314804
Short name T96
Test name
Test status
Simulation time 28390286 ps
CPU time 1.2 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 214784 kb
Host smart-2d47f1d1-e049-4c3e-bb12-a1677f6e7e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154314804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.154314804
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2824877842
Short name T688
Test name
Test status
Simulation time 47632177 ps
CPU time 0.84 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:01 PM PDT 24
Peak memory 206136 kb
Host smart-cd1d58e9-1ead-4a0e-aa9f-dd847b2f25fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824877842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2824877842
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2686959911
Short name T2
Test name
Test status
Simulation time 32312851 ps
CPU time 0.79 seconds
Started Mar 10 01:37:01 PM PDT 24
Finished Mar 10 01:37:04 PM PDT 24
Peak memory 214644 kb
Host smart-0b622f88-c90a-4fc8-8dee-82414db67c03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686959911 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2686959911
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2415949918
Short name T483
Test name
Test status
Simulation time 103978895 ps
CPU time 1.24 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 215424 kb
Host smart-0bf1fb8c-35bc-410a-9bee-dccd873238a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415949918 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2415949918
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1803844766
Short name T46
Test name
Test status
Simulation time 28359324 ps
CPU time 0.9 seconds
Started Mar 10 01:37:01 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 222148 kb
Host smart-94ea720c-19fb-4812-9fa4-0a5853c60713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803844766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1803844766
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1359417836
Short name T733
Test name
Test status
Simulation time 37720178 ps
CPU time 1.38 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:02 PM PDT 24
Peak memory 216604 kb
Host smart-fe9c00b4-253d-4d86-979e-cb5b2b379b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359417836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1359417836
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1435047322
Short name T517
Test name
Test status
Simulation time 41999445 ps
CPU time 1.04 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:05 PM PDT 24
Peak memory 222460 kb
Host smart-d614902d-7ca9-4d1b-9903-8f561aab9a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435047322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1435047322
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3293810648
Short name T797
Test name
Test status
Simulation time 27481365 ps
CPU time 0.95 seconds
Started Mar 10 01:36:59 PM PDT 24
Finished Mar 10 01:37:01 PM PDT 24
Peak memory 214400 kb
Host smart-25c24838-bb93-4377-b1ad-42a5687d73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293810648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3293810648
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2897806638
Short name T196
Test name
Test status
Simulation time 577134098 ps
CPU time 4.1 seconds
Started Mar 10 01:37:02 PM PDT 24
Finished Mar 10 01:37:07 PM PDT 24
Peak memory 214432 kb
Host smart-8152af61-4534-4c5a-8b67-0af9774bf7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897806638 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2897806638
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3868341881
Short name T194
Test name
Test status
Simulation time 127665638592 ps
CPU time 2835.9 seconds
Started Mar 10 01:36:59 PM PDT 24
Finished Mar 10 02:24:15 PM PDT 24
Peak memory 228116 kb
Host smart-1d4f1c5b-a15d-4ee1-9cf3-fe2192312dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868341881 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3868341881
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.843282249
Short name T644
Test name
Test status
Simulation time 26159491 ps
CPU time 1.2 seconds
Started Mar 10 01:38:53 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 216860 kb
Host smart-1ce083a0-3927-486a-895f-04403713159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843282249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.843282249
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2263440782
Short name T605
Test name
Test status
Simulation time 66911333 ps
CPU time 1.17 seconds
Started Mar 10 01:38:55 PM PDT 24
Finished Mar 10 01:38:59 PM PDT 24
Peak memory 215776 kb
Host smart-01d11846-14d3-4dc4-9b9a-222767b59783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263440782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2263440782
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.887757025
Short name T227
Test name
Test status
Simulation time 46131260 ps
CPU time 1.21 seconds
Started Mar 10 01:38:53 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 217156 kb
Host smart-a678f081-4100-4e98-b03d-1143359f941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887757025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.887757025
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2202739173
Short name T521
Test name
Test status
Simulation time 61662295 ps
CPU time 1.32 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 217788 kb
Host smart-13c4db84-16b8-459a-99fb-610d90583d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202739173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2202739173
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3911015387
Short name T477
Test name
Test status
Simulation time 52952814 ps
CPU time 1.86 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 217204 kb
Host smart-d337dfd4-ceb5-472c-a8d4-022e94619f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911015387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3911015387
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3942334318
Short name T705
Test name
Test status
Simulation time 189073324 ps
CPU time 2.72 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:57 PM PDT 24
Peak memory 216996 kb
Host smart-4ba616e9-3e92-4b8d-a9b6-14841c619fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942334318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3942334318
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2261475856
Short name T284
Test name
Test status
Simulation time 50676053 ps
CPU time 1.91 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 216368 kb
Host smart-297e54a5-eaf9-4f6e-ae89-329b1225d4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261475856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2261475856
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2805908535
Short name T423
Test name
Test status
Simulation time 58439510 ps
CPU time 1.72 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 217104 kb
Host smart-3823a931-8d36-4823-a5a4-00333f723bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805908535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2805908535
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1375311844
Short name T484
Test name
Test status
Simulation time 40164141 ps
CPU time 1.59 seconds
Started Mar 10 01:38:52 PM PDT 24
Finished Mar 10 01:38:54 PM PDT 24
Peak memory 216876 kb
Host smart-9fe58de5-a0e2-4674-888f-db0d18a462cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375311844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1375311844
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2524920918
Short name T837
Test name
Test status
Simulation time 52799067 ps
CPU time 1.14 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 215588 kb
Host smart-9d306d51-ac05-427f-a667-6e926f5cebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524920918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2524920918
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2597411384
Short name T609
Test name
Test status
Simulation time 46214206 ps
CPU time 1 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:06 PM PDT 24
Peak memory 206092 kb
Host smart-ce9c5cef-5cd0-4f69-8e33-65bba5d97069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597411384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2597411384
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2726740147
Short name T110
Test name
Test status
Simulation time 42573554 ps
CPU time 0.82 seconds
Started Mar 10 01:37:06 PM PDT 24
Finished Mar 10 01:37:08 PM PDT 24
Peak memory 214908 kb
Host smart-01659122-7578-4d0d-ad17-abf39fd3ae7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726740147 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2726740147
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1339410081
Short name T471
Test name
Test status
Simulation time 26210339 ps
CPU time 1.03 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:01 PM PDT 24
Peak memory 222232 kb
Host smart-eb8cf6c1-8d0a-4a64-9529-e80c77206692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339410081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1339410081
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.906726111
Short name T561
Test name
Test status
Simulation time 24618490 ps
CPU time 1.02 seconds
Started Mar 10 01:37:00 PM PDT 24
Finished Mar 10 01:37:01 PM PDT 24
Peak memory 214536 kb
Host smart-0bf98fa5-f26c-4e09-95bc-de027916d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906726111 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.906726111
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1664736969
Short name T414
Test name
Test status
Simulation time 18466981 ps
CPU time 1.05 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:05 PM PDT 24
Peak memory 214476 kb
Host smart-cf7e069a-e6e9-40af-b00a-814ecf392396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664736969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1664736969
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3709051292
Short name T791
Test name
Test status
Simulation time 167993371 ps
CPU time 3.69 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:10 PM PDT 24
Peak memory 215724 kb
Host smart-f4b334c9-759d-4870-ae1e-78a1358ecfdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709051292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3709051292
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3117793279
Short name T188
Test name
Test status
Simulation time 236111126949 ps
CPU time 1444.55 seconds
Started Mar 10 01:37:08 PM PDT 24
Finished Mar 10 02:01:13 PM PDT 24
Peak memory 222948 kb
Host smart-932a8a5c-acda-4e8f-bb77-7eb75c0ec49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117793279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3117793279
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.743521239
Short name T567
Test name
Test status
Simulation time 28925977 ps
CPU time 1.25 seconds
Started Mar 10 01:38:53 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 215712 kb
Host smart-abf07e43-767b-44bc-8fe0-c210df01507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743521239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.743521239
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1828034636
Short name T386
Test name
Test status
Simulation time 59602695 ps
CPU time 1.14 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 215716 kb
Host smart-228c16d8-5ded-47a6-b7f8-601947611080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828034636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1828034636
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4038784774
Short name T780
Test name
Test status
Simulation time 86194336 ps
CPU time 1.29 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:02 PM PDT 24
Peak memory 216932 kb
Host smart-e40fea8f-ca62-4a50-ba23-cae455de864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038784774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4038784774
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3786284365
Short name T422
Test name
Test status
Simulation time 51998322 ps
CPU time 1.78 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 215776 kb
Host smart-f0f0de40-02e6-4eed-82f5-8ff47ada43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786284365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3786284365
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1541066326
Short name T503
Test name
Test status
Simulation time 71821934 ps
CPU time 2.87 seconds
Started Mar 10 01:38:50 PM PDT 24
Finished Mar 10 01:38:54 PM PDT 24
Peak memory 216740 kb
Host smart-97de4595-684b-43c7-aef6-152aafad5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541066326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1541066326
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.4098579580
Short name T519
Test name
Test status
Simulation time 60635757 ps
CPU time 1.34 seconds
Started Mar 10 01:38:56 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 215516 kb
Host smart-ad3083cc-4bd0-47be-ad43-e9ff6f96a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098579580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.4098579580
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3548516007
Short name T631
Test name
Test status
Simulation time 55473310 ps
CPU time 1.5 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 218524 kb
Host smart-122a2161-5f88-4f65-aba3-c28b584b1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548516007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3548516007
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2012101369
Short name T177
Test name
Test status
Simulation time 75432490 ps
CPU time 1.21 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 215696 kb
Host smart-eab11822-8d1d-4295-afd4-27775abb8b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012101369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2012101369
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3797661244
Short name T700
Test name
Test status
Simulation time 150388429 ps
CPU time 1.33 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 215788 kb
Host smart-06b52724-e1f4-4179-af7e-ef74946bf701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797661244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3797661244
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1286917221
Short name T446
Test name
Test status
Simulation time 86345947 ps
CPU time 1.61 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 217516 kb
Host smart-21830d58-8bcf-4020-9023-e9649d9b626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286917221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1286917221
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1544377326
Short name T102
Test name
Test status
Simulation time 29476831 ps
CPU time 1.28 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:07 PM PDT 24
Peak memory 214696 kb
Host smart-5a998287-5b7b-47bb-a2b3-24a7d0d8f4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544377326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1544377326
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2076584212
Short name T502
Test name
Test status
Simulation time 51044783 ps
CPU time 0.91 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:07 PM PDT 24
Peak memory 205688 kb
Host smart-293d22d1-9ebf-4a9b-a58e-8e801e1cff50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076584212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2076584212
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3512684454
Short name T417
Test name
Test status
Simulation time 15721856 ps
CPU time 0.84 seconds
Started Mar 10 01:37:07 PM PDT 24
Finished Mar 10 01:37:09 PM PDT 24
Peak memory 214632 kb
Host smart-8c776db2-9d2f-4329-ac10-114abe627721
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512684454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3512684454
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4196833835
Short name T174
Test name
Test status
Simulation time 26223021 ps
CPU time 0.99 seconds
Started Mar 10 01:37:05 PM PDT 24
Finished Mar 10 01:37:07 PM PDT 24
Peak memory 215348 kb
Host smart-4f08e679-9515-4b80-8d14-b0a6fd185444
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196833835 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4196833835
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2111328164
Short name T98
Test name
Test status
Simulation time 31453337 ps
CPU time 0.89 seconds
Started Mar 10 01:37:06 PM PDT 24
Finished Mar 10 01:37:08 PM PDT 24
Peak memory 217056 kb
Host smart-3a23a8bd-7a8c-46d9-ab59-bc98f9add7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111328164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2111328164
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.23080605
Short name T464
Test name
Test status
Simulation time 63018629 ps
CPU time 1.6 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:06 PM PDT 24
Peak memory 216892 kb
Host smart-13bc5c95-5a6e-44e7-9c1d-d28349bee297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23080605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.23080605
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.937504542
Short name T126
Test name
Test status
Simulation time 26589372 ps
CPU time 0.91 seconds
Started Mar 10 01:37:08 PM PDT 24
Finished Mar 10 01:37:09 PM PDT 24
Peak memory 214704 kb
Host smart-ed2d39d3-7684-4c83-b845-7fc0f9abac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937504542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.937504542
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.383926198
Short name T737
Test name
Test status
Simulation time 32160766 ps
CPU time 0.93 seconds
Started Mar 10 01:37:06 PM PDT 24
Finished Mar 10 01:37:09 PM PDT 24
Peak memory 214428 kb
Host smart-c60f1046-28b4-4a2f-aa0c-6315b464bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383926198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.383926198
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2810937878
Short name T138
Test name
Test status
Simulation time 690984384 ps
CPU time 3.27 seconds
Started Mar 10 01:37:06 PM PDT 24
Finished Mar 10 01:37:10 PM PDT 24
Peak memory 214408 kb
Host smart-9d6bf0f8-9648-4aae-9767-6135f694a03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810937878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2810937878
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2239436919
Short name T742
Test name
Test status
Simulation time 117842339284 ps
CPU time 741.75 seconds
Started Mar 10 01:37:06 PM PDT 24
Finished Mar 10 01:49:29 PM PDT 24
Peak memory 220628 kb
Host smart-e9173b96-0fb6-405e-a5af-7f8395413a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239436919 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2239436919
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1041547447
Short name T493
Test name
Test status
Simulation time 119326104 ps
CPU time 1.19 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 217856 kb
Host smart-1f6d3893-bb5d-47be-ba0a-109c180bb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041547447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1041547447
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4210169145
Short name T774
Test name
Test status
Simulation time 31578691 ps
CPU time 1.25 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:53 PM PDT 24
Peak memory 216844 kb
Host smart-bbfb7276-a907-456f-8ce2-9be1de7edf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210169145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4210169145
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2774494103
Short name T353
Test name
Test status
Simulation time 66780013 ps
CPU time 1.26 seconds
Started Mar 10 01:38:52 PM PDT 24
Finished Mar 10 01:38:54 PM PDT 24
Peak memory 215592 kb
Host smart-0c7f4fce-285f-4c8b-b9fe-52d086b9e3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774494103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2774494103
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.290619254
Short name T758
Test name
Test status
Simulation time 40735958 ps
CPU time 1.06 seconds
Started Mar 10 01:38:55 PM PDT 24
Finished Mar 10 01:38:59 PM PDT 24
Peak memory 215700 kb
Host smart-4abbf19f-3759-4df9-8d5f-b4f9b9d91961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290619254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.290619254
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3572588725
Short name T834
Test name
Test status
Simulation time 57918748 ps
CPU time 1.23 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 214388 kb
Host smart-536851ce-24cb-4f74-9bd9-043d91df73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572588725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3572588725
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3184622672
Short name T264
Test name
Test status
Simulation time 182501975 ps
CPU time 2.45 seconds
Started Mar 10 01:38:55 PM PDT 24
Finished Mar 10 01:39:01 PM PDT 24
Peak memory 215996 kb
Host smart-eec9da5c-9d11-4362-aecb-d6cc6fc64da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184622672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3184622672
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.634545550
Short name T494
Test name
Test status
Simulation time 287793289 ps
CPU time 4.06 seconds
Started Mar 10 01:38:52 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 218512 kb
Host smart-455e3229-0394-4804-90fc-6ca134da23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634545550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.634545550
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2353444180
Short name T585
Test name
Test status
Simulation time 47636996 ps
CPU time 1.18 seconds
Started Mar 10 01:38:53 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 217176 kb
Host smart-0b5ce297-5a1e-410d-9843-f2deeddd136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353444180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2353444180
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3492220228
Short name T442
Test name
Test status
Simulation time 70512164 ps
CPU time 2.53 seconds
Started Mar 10 01:38:50 PM PDT 24
Finished Mar 10 01:38:54 PM PDT 24
Peak memory 215868 kb
Host smart-3c4e7f25-f6c5-46c3-9274-12e6f648d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492220228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3492220228
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.735326779
Short name T425
Test name
Test status
Simulation time 58218085 ps
CPU time 1.64 seconds
Started Mar 10 01:38:55 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 217032 kb
Host smart-020fd001-e313-4d6b-ba97-49d3ae730afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735326779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.735326779
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3582567052
Short name T591
Test name
Test status
Simulation time 377836878 ps
CPU time 1.61 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:13 PM PDT 24
Peak memory 214748 kb
Host smart-ce33767a-d4e1-4a40-b5d3-80993118ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582567052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3582567052
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3912681272
Short name T748
Test name
Test status
Simulation time 17315303 ps
CPU time 0.81 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 204992 kb
Host smart-a375d33c-3e0d-4163-aa3c-12794af9fbeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912681272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3912681272
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3128573540
Short name T795
Test name
Test status
Simulation time 45564121 ps
CPU time 0.86 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 214652 kb
Host smart-4cc8815c-3355-44fd-9420-3a1276325d63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128573540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3128573540
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.865618253
Short name T451
Test name
Test status
Simulation time 46769982 ps
CPU time 1.05 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:12 PM PDT 24
Peak memory 216940 kb
Host smart-9f949925-c80a-4f63-8632-9f88bef606e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865618253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.865618253
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1566886795
Short name T225
Test name
Test status
Simulation time 44228135 ps
CPU time 0.96 seconds
Started Mar 10 01:37:13 PM PDT 24
Finished Mar 10 01:37:14 PM PDT 24
Peak memory 216988 kb
Host smart-955a0a1f-4a95-4eb3-a523-c37c4e8daf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566886795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1566886795
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2613806821
Short name T640
Test name
Test status
Simulation time 123597796 ps
CPU time 1.2 seconds
Started Mar 10 01:37:03 PM PDT 24
Finished Mar 10 01:37:04 PM PDT 24
Peak memory 215772 kb
Host smart-4fe9339a-e3aa-4cd4-a873-645b6c1a0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613806821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2613806821
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2145811942
Short name T556
Test name
Test status
Simulation time 51898409 ps
CPU time 1 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 222336 kb
Host smart-df06e5e6-7e60-4d2e-9079-0bfac833ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145811942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2145811942
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3706667249
Short name T382
Test name
Test status
Simulation time 32507033 ps
CPU time 0.97 seconds
Started Mar 10 01:37:07 PM PDT 24
Finished Mar 10 01:37:09 PM PDT 24
Peak memory 206184 kb
Host smart-8fd36b11-7a36-4ad1-829a-b013aaeaed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706667249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3706667249
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3197755391
Short name T43
Test name
Test status
Simulation time 148333097 ps
CPU time 1.94 seconds
Started Mar 10 01:37:04 PM PDT 24
Finished Mar 10 01:37:06 PM PDT 24
Peak memory 214476 kb
Host smart-e1653cdb-cd66-4a0c-8103-ba1526868d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197755391 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3197755391
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3539524890
Short name T142
Test name
Test status
Simulation time 27075097783 ps
CPU time 533.07 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:46:05 PM PDT 24
Peak memory 222864 kb
Host smart-1b4e8812-5101-4dea-aa0a-8ef7c9dc19cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539524890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3539524890
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2186835313
Short name T434
Test name
Test status
Simulation time 142911562 ps
CPU time 3.23 seconds
Started Mar 10 01:38:51 PM PDT 24
Finished Mar 10 01:38:55 PM PDT 24
Peak memory 217740 kb
Host smart-da0c3a21-1f5a-4f8e-9257-362be96668ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186835313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2186835313
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.287834291
Short name T619
Test name
Test status
Simulation time 131548865 ps
CPU time 1.32 seconds
Started Mar 10 01:38:54 PM PDT 24
Finished Mar 10 01:38:56 PM PDT 24
Peak memory 218528 kb
Host smart-59a10b22-62ce-4d80-87bd-5e7b8d49cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287834291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.287834291
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3929248260
Short name T350
Test name
Test status
Simulation time 153806582 ps
CPU time 1.37 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:05 PM PDT 24
Peak memory 217468 kb
Host smart-893314cf-df66-44c8-97bd-34dd6b341ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929248260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3929248260
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3950419963
Short name T323
Test name
Test status
Simulation time 41819434 ps
CPU time 1.42 seconds
Started Mar 10 01:38:59 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 215736 kb
Host smart-38a3b7f9-2e5e-4621-b54f-b5912d3346ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950419963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3950419963
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3247372740
Short name T279
Test name
Test status
Simulation time 68039020 ps
CPU time 1.38 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:02 PM PDT 24
Peak memory 217324 kb
Host smart-bfd76ffa-b70a-46ea-87f0-f76bf5ac7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247372740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3247372740
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3015542470
Short name T328
Test name
Test status
Simulation time 28880273 ps
CPU time 1.13 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 215716 kb
Host smart-b6108e7e-98fb-4d23-b7ef-cd926b1e4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015542470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3015542470
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2139634157
Short name T731
Test name
Test status
Simulation time 55055575 ps
CPU time 1.24 seconds
Started Mar 10 01:38:57 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 218184 kb
Host smart-10b63acb-2f8f-44f1-a2c3-ab9a9df73742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139634157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2139634157
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1426679022
Short name T374
Test name
Test status
Simulation time 52025464 ps
CPU time 1.21 seconds
Started Mar 10 01:39:00 PM PDT 24
Finished Mar 10 01:39:02 PM PDT 24
Peak memory 216600 kb
Host smart-6d08df00-d153-4730-86d5-92a4e9f5055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426679022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1426679022
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2405199583
Short name T474
Test name
Test status
Simulation time 42355465 ps
CPU time 1.71 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 216944 kb
Host smart-035f87b9-d54a-4fdf-9a0f-4e3b65e4210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405199583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2405199583
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1547733056
Short name T818
Test name
Test status
Simulation time 99800807 ps
CPU time 2.59 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 216936 kb
Host smart-b39b71d8-af10-46e1-978c-d3181098fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547733056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1547733056
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1112257588
Short name T255
Test name
Test status
Simulation time 30296089 ps
CPU time 1.32 seconds
Started Mar 10 01:37:12 PM PDT 24
Finished Mar 10 01:37:14 PM PDT 24
Peak memory 214740 kb
Host smart-45d2918a-9d2b-403d-8a66-8beb308625e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112257588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1112257588
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.142742418
Short name T651
Test name
Test status
Simulation time 138696112 ps
CPU time 0.86 seconds
Started Mar 10 01:37:12 PM PDT 24
Finished Mar 10 01:37:13 PM PDT 24
Peak memory 205976 kb
Host smart-cfd68caf-3361-4682-ad88-1b457bdfce7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142742418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.142742418
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.114752264
Short name T807
Test name
Test status
Simulation time 15305262 ps
CPU time 0.87 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:12 PM PDT 24
Peak memory 214560 kb
Host smart-47c79368-7dd3-46f0-b48a-549398542e3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114752264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.114752264
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.784645159
Short name T817
Test name
Test status
Simulation time 141508865 ps
CPU time 1.29 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 215408 kb
Host smart-18078c3e-c1ea-4b2c-97a1-d549cd4e445d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784645159 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.784645159
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2615475662
Short name T97
Test name
Test status
Simulation time 31285864 ps
CPU time 0.8 seconds
Started Mar 10 01:37:09 PM PDT 24
Finished Mar 10 01:37:10 PM PDT 24
Peak memory 217016 kb
Host smart-7018ae1a-79d7-419c-ac39-2e6e4994a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615475662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2615475662
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3981552939
Short name T727
Test name
Test status
Simulation time 60839684 ps
CPU time 1.84 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:13 PM PDT 24
Peak memory 216756 kb
Host smart-6bab071e-46db-4cb8-9170-1442790982a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981552939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3981552939
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.44127325
Short name T755
Test name
Test status
Simulation time 30147922 ps
CPU time 0.97 seconds
Started Mar 10 01:37:09 PM PDT 24
Finished Mar 10 01:37:10 PM PDT 24
Peak memory 214752 kb
Host smart-7edd7e33-bfa2-4663-814a-45c0cae5042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44127325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.44127325
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.22874174
Short name T344
Test name
Test status
Simulation time 76587611 ps
CPU time 0.94 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 214420 kb
Host smart-1a888959-17c7-45ae-9f62-0600903d9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22874174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.22874174
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2102982267
Short name T703
Test name
Test status
Simulation time 2920781408 ps
CPU time 5.12 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 215796 kb
Host smart-dce8a5e9-bd61-4401-a5be-ab83c3b63df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102982267 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2102982267
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1343879798
Short name T421
Test name
Test status
Simulation time 5041389875 ps
CPU time 130.81 seconds
Started Mar 10 01:37:12 PM PDT 24
Finished Mar 10 01:39:23 PM PDT 24
Peak memory 215988 kb
Host smart-2d72b165-a38d-4de2-8555-9b9dc13c04ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343879798 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1343879798
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2056743168
Short name T689
Test name
Test status
Simulation time 248946542 ps
CPU time 0.99 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215664 kb
Host smart-5c8f5136-4955-459b-8b53-6bf22c998cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056743168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2056743168
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.455192496
Short name T53
Test name
Test status
Simulation time 78079024 ps
CPU time 1.06 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 215536 kb
Host smart-5e878d0a-4dca-40bb-b43a-5f6b9b9162f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455192496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.455192496
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1885898719
Short name T270
Test name
Test status
Simulation time 65502254 ps
CPU time 1.55 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 216816 kb
Host smart-45b0d132-6166-4046-bec1-afc75e689e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885898719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1885898719
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2608188991
Short name T712
Test name
Test status
Simulation time 89341671 ps
CPU time 1.25 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:08 PM PDT 24
Peak memory 217276 kb
Host smart-2b1e7efe-4383-488a-82ae-78afeeb9b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608188991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2608188991
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2976264545
Short name T40
Test name
Test status
Simulation time 115623173 ps
CPU time 1.54 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 215796 kb
Host smart-ca18bfbc-5fba-48a2-81eb-181d9e6a5709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976264545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2976264545
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1273808784
Short name T562
Test name
Test status
Simulation time 49327465 ps
CPU time 1.59 seconds
Started Mar 10 01:38:55 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 216824 kb
Host smart-0f786da8-c52b-4d27-98e2-b46628ff05e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273808784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1273808784
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2136650208
Short name T613
Test name
Test status
Simulation time 65342799 ps
CPU time 1.57 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 217168 kb
Host smart-ed1ec0ed-9472-417c-97c5-b6b74a3fc534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136650208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2136650208
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2887476447
Short name T401
Test name
Test status
Simulation time 73376142 ps
CPU time 1.02 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215656 kb
Host smart-56ac0873-03ea-40dd-9591-7dc52bb47dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887476447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2887476447
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1149206698
Short name T565
Test name
Test status
Simulation time 260498076 ps
CPU time 3.89 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 216036 kb
Host smart-b69982ea-5b8e-4c0c-90e0-df0a5c9996e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149206698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1149206698
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.311441519
Short name T684
Test name
Test status
Simulation time 14908083 ps
CPU time 0.94 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:18 PM PDT 24
Peak memory 205700 kb
Host smart-3c8cb968-d188-480d-871c-8129272abc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311441519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.311441519
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2991836436
Short name T195
Test name
Test status
Simulation time 22838647 ps
CPU time 0.93 seconds
Started Mar 10 01:37:12 PM PDT 24
Finished Mar 10 01:37:13 PM PDT 24
Peak memory 214520 kb
Host smart-4c81e485-f8d4-4eb5-90f2-107ccb99e382
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991836436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2991836436
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4032847825
Short name T465
Test name
Test status
Simulation time 105316718 ps
CPU time 1.11 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 215516 kb
Host smart-b1ef6823-4d9b-49e6-b5c4-6d0fd2e2a5e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032847825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4032847825
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.73965397
Short name T17
Test name
Test status
Simulation time 19888417 ps
CPU time 1.22 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:18 PM PDT 24
Peak memory 222368 kb
Host smart-a40e19f0-7b19-4455-9794-f08f47e2ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73965397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.73965397
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1072330340
Short name T677
Test name
Test status
Simulation time 38196664 ps
CPU time 1.06 seconds
Started Mar 10 01:37:10 PM PDT 24
Finished Mar 10 01:37:11 PM PDT 24
Peak memory 215724 kb
Host smart-ebe7b647-13bb-4d35-aef3-2ae479e6a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072330340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1072330340
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2295554119
Short name T674
Test name
Test status
Simulation time 20773172 ps
CPU time 1.11 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 214748 kb
Host smart-462ff4e4-6a1f-48ff-b49f-2ad9cd243ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295554119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2295554119
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3134413107
Short name T324
Test name
Test status
Simulation time 17102746 ps
CPU time 0.98 seconds
Started Mar 10 01:37:11 PM PDT 24
Finished Mar 10 01:37:12 PM PDT 24
Peak memory 214396 kb
Host smart-a896fbe6-7973-4d3b-89e8-38e00387cdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134413107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3134413107
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.652453531
Short name T346
Test name
Test status
Simulation time 142057204 ps
CPU time 2 seconds
Started Mar 10 01:37:12 PM PDT 24
Finished Mar 10 01:37:14 PM PDT 24
Peak memory 215400 kb
Host smart-1aaf2f67-c0a2-408b-b402-2308dae6fdcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652453531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.652453531
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.978479356
Short name T455
Test name
Test status
Simulation time 126637780805 ps
CPU time 1456.76 seconds
Started Mar 10 01:37:13 PM PDT 24
Finished Mar 10 02:01:30 PM PDT 24
Peak memory 222200 kb
Host smart-b9757343-7420-414b-a165-284d66f212ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978479356 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.978479356
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.92095193
Short name T234
Test name
Test status
Simulation time 30413651 ps
CPU time 1.05 seconds
Started Mar 10 01:39:00 PM PDT 24
Finished Mar 10 01:39:01 PM PDT 24
Peak memory 215636 kb
Host smart-013ee707-08c3-4a8e-9dfc-2dbde2f09b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92095193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.92095193
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2344687738
Short name T277
Test name
Test status
Simulation time 36688201 ps
CPU time 1.42 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215768 kb
Host smart-28c0fe57-aac1-4e23-9f73-1c82f6c3358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344687738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2344687738
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1298903678
Short name T226
Test name
Test status
Simulation time 53179088 ps
CPU time 1.92 seconds
Started Mar 10 01:38:58 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 216980 kb
Host smart-2792793f-9752-4f50-bdc0-0e2f72ca7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298903678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1298903678
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.185724159
Short name T463
Test name
Test status
Simulation time 34775144 ps
CPU time 1.22 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215540 kb
Host smart-ffa7d683-0188-4e11-99ed-5cb7b05dea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185724159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.185724159
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.949915461
Short name T577
Test name
Test status
Simulation time 36595078 ps
CPU time 1.7 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:05 PM PDT 24
Peak memory 216996 kb
Host smart-c8c0bb29-939f-4414-b8f4-2b3f157eb44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949915461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.949915461
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1454247499
Short name T815
Test name
Test status
Simulation time 47290750 ps
CPU time 1.52 seconds
Started Mar 10 01:38:58 PM PDT 24
Finished Mar 10 01:39:00 PM PDT 24
Peak memory 214448 kb
Host smart-980f4c19-5731-45fb-b3ee-22bb48774fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454247499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1454247499
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2856947839
Short name T634
Test name
Test status
Simulation time 73103783 ps
CPU time 2.63 seconds
Started Mar 10 01:39:01 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 216924 kb
Host smart-9f272bc0-f985-4d85-979f-3f4f9b18c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856947839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2856947839
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3637660872
Short name T650
Test name
Test status
Simulation time 92830719 ps
CPU time 1.27 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 217552 kb
Host smart-41d78877-fc91-4bca-9410-32d4eeb7ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637660872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3637660872
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.993753415
Short name T792
Test name
Test status
Simulation time 122783350 ps
CPU time 1.52 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 216964 kb
Host smart-c6810f55-1076-4e54-af66-6e3cb117450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993753415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.993753415
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1435690259
Short name T497
Test name
Test status
Simulation time 77909985 ps
CPU time 1.23 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 217128 kb
Host smart-f8aa926d-d8c1-454b-83e5-eb96b6707535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435690259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1435690259
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.223755539
Short name T793
Test name
Test status
Simulation time 26695610 ps
CPU time 1.28 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 214752 kb
Host smart-d2eb486f-b4e3-4f71-8145-72c5fa81e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223755539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.223755539
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2565578475
Short name T151
Test name
Test status
Simulation time 117824501 ps
CPU time 2.25 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:22 PM PDT 24
Peak memory 206296 kb
Host smart-ffa21635-4e85-44f7-96eb-e49063497674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565578475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2565578475
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.944487553
Short name T106
Test name
Test status
Simulation time 20126304 ps
CPU time 0.93 seconds
Started Mar 10 01:37:17 PM PDT 24
Finished Mar 10 01:37:18 PM PDT 24
Peak memory 214864 kb
Host smart-0de16382-4696-4279-9292-378f389694c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944487553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.944487553
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2841730662
Short name T738
Test name
Test status
Simulation time 99466288 ps
CPU time 1.03 seconds
Started Mar 10 01:37:17 PM PDT 24
Finished Mar 10 01:37:18 PM PDT 24
Peak memory 216556 kb
Host smart-e40a9ce8-42fe-441f-95cf-5c73abe537a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841730662 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2841730662
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2411323737
Short name T75
Test name
Test status
Simulation time 24589908 ps
CPU time 1.31 seconds
Started Mar 10 01:37:19 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 229100 kb
Host smart-a16ebcc9-e6ab-4d60-86aa-b302cce3a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411323737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2411323737
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2653859044
Short name T475
Test name
Test status
Simulation time 108483404 ps
CPU time 1.19 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 215784 kb
Host smart-d1a48f8c-d19e-46d8-9286-368ea716857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653859044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2653859044
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4173782411
Short name T500
Test name
Test status
Simulation time 20710927 ps
CPU time 1.1 seconds
Started Mar 10 01:37:15 PM PDT 24
Finished Mar 10 01:37:16 PM PDT 24
Peak memory 214564 kb
Host smart-609a15ac-3f21-4e3f-a2b8-8470f92b77bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173782411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4173782411
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1533301568
Short name T296
Test name
Test status
Simulation time 17712830 ps
CPU time 0.96 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 214420 kb
Host smart-40bd12f2-132c-4878-bfee-e3524cc2e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533301568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1533301568
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2415429679
Short name T364
Test name
Test status
Simulation time 117994019 ps
CPU time 1.26 seconds
Started Mar 10 01:37:18 PM PDT 24
Finished Mar 10 01:37:19 PM PDT 24
Peak memory 214368 kb
Host smart-0f6e2eff-2b5c-49ae-8041-ff9f8fb04532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415429679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2415429679
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2869268145
Short name T224
Test name
Test status
Simulation time 464194121647 ps
CPU time 1676.09 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 02:05:13 PM PDT 24
Peak memory 223260 kb
Host smart-34a74a04-d3d5-4c23-9d62-f7e3a27b5e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869268145 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2869268145
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.208474105
Short name T555
Test name
Test status
Simulation time 45546231 ps
CPU time 0.99 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 215636 kb
Host smart-60b3f38a-8041-46e3-9677-75a84a8f67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208474105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.208474105
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1453364174
Short name T616
Test name
Test status
Simulation time 73062568 ps
CPU time 1.36 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 216964 kb
Host smart-7159b15c-1262-40ec-bf6f-cc9acfe41464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453364174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1453364174
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.217762479
Short name T764
Test name
Test status
Simulation time 80786156 ps
CPU time 1.14 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215820 kb
Host smart-c2f0783b-7327-4e3f-bdc6-67ef942565a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217762479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.217762479
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3287988819
Short name T622
Test name
Test status
Simulation time 32304452 ps
CPU time 1.38 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 218356 kb
Host smart-a9d434ff-7a73-4585-a25a-790e864647a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287988819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3287988819
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1754048670
Short name T140
Test name
Test status
Simulation time 68254299 ps
CPU time 1.43 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 217316 kb
Host smart-09dba0ef-1ee0-41e7-97a7-2d50e87feece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754048670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1754048670
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2164346724
Short name T681
Test name
Test status
Simulation time 44489674 ps
CPU time 1.49 seconds
Started Mar 10 01:39:04 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 216904 kb
Host smart-c94178d9-404c-4f84-b495-e341806bdc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164346724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2164346724
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4197254228
Short name T313
Test name
Test status
Simulation time 36371879 ps
CPU time 1.5 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 217036 kb
Host smart-0967b606-078b-49fe-a9a5-b9d084544775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197254228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4197254228
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.740509861
Short name T456
Test name
Test status
Simulation time 37905809 ps
CPU time 1.15 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215644 kb
Host smart-7a7f6fd2-de43-47b1-b0ee-3fe940961245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740509861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.740509861
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.4227556757
Short name T673
Test name
Test status
Simulation time 71555012 ps
CPU time 1.23 seconds
Started Mar 10 01:39:05 PM PDT 24
Finished Mar 10 01:39:07 PM PDT 24
Peak memory 217264 kb
Host smart-1af5c12a-4f49-451e-ab80-d7ebcc0a33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227556757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4227556757
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.240036006
Short name T636
Test name
Test status
Simulation time 42490373 ps
CPU time 1.46 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 216796 kb
Host smart-564720cd-3229-4447-8f76-344eb1677bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240036006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.240036006
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2662195681
Short name T147
Test name
Test status
Simulation time 80720911 ps
CPU time 1.25 seconds
Started Mar 10 01:37:19 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 214820 kb
Host smart-a7c8b45e-d8bf-444d-a8f2-7ff7751a80df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662195681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2662195681
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1503236909
Short name T801
Test name
Test status
Simulation time 42349733 ps
CPU time 0.78 seconds
Started Mar 10 01:37:25 PM PDT 24
Finished Mar 10 01:37:26 PM PDT 24
Peak memory 204932 kb
Host smart-e63b9027-2c02-4578-847f-69b7c48b6ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503236909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1503236909
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_err.1675373834
Short name T647
Test name
Test status
Simulation time 20986289 ps
CPU time 1.16 seconds
Started Mar 10 01:37:18 PM PDT 24
Finished Mar 10 01:37:20 PM PDT 24
Peak memory 218416 kb
Host smart-95f22238-6155-4198-9eb8-32fcef08b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675373834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1675373834
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3304968527
Short name T685
Test name
Test status
Simulation time 29295331 ps
CPU time 1.34 seconds
Started Mar 10 01:37:18 PM PDT 24
Finished Mar 10 01:37:20 PM PDT 24
Peak memory 217988 kb
Host smart-c91da5fe-7f9a-4437-9406-9ab867a807f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304968527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3304968527
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1224524156
Short name T523
Test name
Test status
Simulation time 26407541 ps
CPU time 0.85 seconds
Started Mar 10 01:37:16 PM PDT 24
Finished Mar 10 01:37:17 PM PDT 24
Peak memory 214684 kb
Host smart-1d4fe0bd-872b-4b66-8cb6-782a06b3bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224524156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1224524156
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2605985874
Short name T342
Test name
Test status
Simulation time 24729884 ps
CPU time 0.96 seconds
Started Mar 10 01:37:18 PM PDT 24
Finished Mar 10 01:37:19 PM PDT 24
Peak memory 214444 kb
Host smart-4fff4f93-847c-4d86-bb3b-f5d9f040c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605985874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2605985874
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1183524085
Short name T438
Test name
Test status
Simulation time 309408987 ps
CPU time 5.89 seconds
Started Mar 10 01:37:17 PM PDT 24
Finished Mar 10 01:37:23 PM PDT 24
Peak memory 216780 kb
Host smart-2b86a717-a5f4-4697-b9d2-8cd35ad6bc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183524085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1183524085
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.276477613
Short name T670
Test name
Test status
Simulation time 26672493848 ps
CPU time 568.5 seconds
Started Mar 10 01:37:21 PM PDT 24
Finished Mar 10 01:46:50 PM PDT 24
Peak memory 216692 kb
Host smart-905fdb50-2dfd-45a5-90d3-ab3afa0cc66e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276477613 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.276477613
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.338921710
Short name T222
Test name
Test status
Simulation time 90601015 ps
CPU time 1.27 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 217028 kb
Host smart-a0452073-037c-4393-8272-6c5da6eb61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338921710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.338921710
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2077451169
Short name T287
Test name
Test status
Simulation time 46834051 ps
CPU time 1.61 seconds
Started Mar 10 01:39:00 PM PDT 24
Finished Mar 10 01:39:01 PM PDT 24
Peak memory 217884 kb
Host smart-fec1f18b-24d6-4a59-a49d-83e4ea1057a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077451169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2077451169
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.928791063
Short name T637
Test name
Test status
Simulation time 17444559 ps
CPU time 1.03 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 218168 kb
Host smart-238b360d-c3b6-4b2a-ae13-549319722315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928791063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.928791063
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.851765927
Short name T573
Test name
Test status
Simulation time 49235313 ps
CPU time 1.43 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 217460 kb
Host smart-05bceba6-9214-4138-b79d-9d3221745c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851765927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.851765927
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3965000688
Short name T15
Test name
Test status
Simulation time 88742018 ps
CPU time 3.05 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:11 PM PDT 24
Peak memory 217116 kb
Host smart-edc19dc3-3c73-4adb-a301-7714575214ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965000688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3965000688
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3064879323
Short name T361
Test name
Test status
Simulation time 82497390 ps
CPU time 1.63 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 216940 kb
Host smart-7ad247ee-8ac5-44e6-87a4-8b8a85aa3d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064879323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3064879323
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4289346272
Short name T283
Test name
Test status
Simulation time 90032930 ps
CPU time 1.05 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:04 PM PDT 24
Peak memory 215668 kb
Host smart-a108829e-ceda-4f6c-b8d1-5fb66cc96093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289346272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4289346272
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1460559854
Short name T291
Test name
Test status
Simulation time 107814227 ps
CPU time 1.5 seconds
Started Mar 10 01:39:04 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 217560 kb
Host smart-111ea822-9b29-4a33-902c-7f41973e36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460559854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1460559854
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3379613241
Short name T496
Test name
Test status
Simulation time 157144138 ps
CPU time 3.66 seconds
Started Mar 10 01:39:03 PM PDT 24
Finished Mar 10 01:39:07 PM PDT 24
Peak memory 218528 kb
Host smart-9a39b0bf-14fa-464f-88f4-e04c2e80accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379613241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3379613241
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1662759099
Short name T560
Test name
Test status
Simulation time 64979032 ps
CPU time 1.37 seconds
Started Mar 10 01:39:02 PM PDT 24
Finished Mar 10 01:39:03 PM PDT 24
Peak memory 214420 kb
Host smart-f7894cde-baa2-4926-8245-6a3210b22db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662759099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1662759099
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3945559001
Short name T261
Test name
Test status
Simulation time 49256599 ps
CPU time 1.32 seconds
Started Mar 10 01:37:21 PM PDT 24
Finished Mar 10 01:37:22 PM PDT 24
Peak memory 214764 kb
Host smart-27418b4a-c4eb-46c5-a1d6-164847bc4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945559001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3945559001
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2813296163
Short name T524
Test name
Test status
Simulation time 22347004 ps
CPU time 0.83 seconds
Started Mar 10 01:37:22 PM PDT 24
Finished Mar 10 01:37:23 PM PDT 24
Peak memory 205124 kb
Host smart-fbf63574-2d97-49f7-acd9-fe83aaa7d7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813296163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2813296163
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1107928321
Short name T168
Test name
Test status
Simulation time 28472467 ps
CPU time 0.86 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 214888 kb
Host smart-5dfde7a5-f326-47c8-ba6c-031301b21ab3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107928321 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1107928321
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2332769745
Short name T317
Test name
Test status
Simulation time 19086973 ps
CPU time 1.05 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:26 PM PDT 24
Peak memory 216804 kb
Host smart-0ea2da6b-36aa-45d0-9c84-04e96d198ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332769745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2332769745
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.590669004
Short name T796
Test name
Test status
Simulation time 55101966 ps
CPU time 1.74 seconds
Started Mar 10 01:37:25 PM PDT 24
Finished Mar 10 01:37:27 PM PDT 24
Peak memory 216840 kb
Host smart-62236377-efbc-4bcf-b1ed-c331c613a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590669004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.590669004
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1725709526
Short name T498
Test name
Test status
Simulation time 21836897 ps
CPU time 1.12 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 214684 kb
Host smart-fea5b709-ab5a-4d8a-aefe-dcf452736fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725709526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1725709526
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2307518446
Short name T549
Test name
Test status
Simulation time 15547119 ps
CPU time 1 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 214340 kb
Host smart-ba13d52b-65f5-482b-a200-b45fcc97e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307518446 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2307518446
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1527280279
Short name T788
Test name
Test status
Simulation time 107874155 ps
CPU time 1.63 seconds
Started Mar 10 01:37:22 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 215632 kb
Host smart-2168b1c8-2d4a-4037-99b0-8557b5d2c6a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527280279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1527280279
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.921277351
Short name T27
Test name
Test status
Simulation time 31720310494 ps
CPU time 667.34 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:48:28 PM PDT 24
Peak memory 218860 kb
Host smart-083fd9da-0de9-4c08-ac9a-138c749d3f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921277351 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.921277351
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2819310699
Short name T339
Test name
Test status
Simulation time 64230747 ps
CPU time 1.34 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:08 PM PDT 24
Peak memory 216692 kb
Host smart-f6918d3b-87d4-498d-92c9-ce3e4f1f0917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819310699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2819310699
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2193856489
Short name T786
Test name
Test status
Simulation time 31450376 ps
CPU time 1.33 seconds
Started Mar 10 01:39:09 PM PDT 24
Finished Mar 10 01:39:11 PM PDT 24
Peak memory 217032 kb
Host smart-b91e0db0-1709-4dd5-b413-d218d1bbc1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193856489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2193856489
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3940328864
Short name T828
Test name
Test status
Simulation time 43433624 ps
CPU time 1.58 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 217052 kb
Host smart-85e31fe4-eb6e-4564-9a30-8d992e0765f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940328864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3940328864
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.549723581
Short name T825
Test name
Test status
Simulation time 47935402 ps
CPU time 1.62 seconds
Started Mar 10 01:39:05 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 216996 kb
Host smart-bafbc60f-fabf-4584-b6e6-a9cfe3143fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549723581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.549723581
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2447410378
Short name T770
Test name
Test status
Simulation time 62679224 ps
CPU time 1.38 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 216784 kb
Host smart-14ad41cd-7070-463b-b41f-1842f6cdcee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447410378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2447410378
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.316373038
Short name T652
Test name
Test status
Simulation time 301306628 ps
CPU time 1.22 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 214388 kb
Host smart-06083d06-8b48-4c93-b099-d4919b8c568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316373038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.316373038
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1114921882
Short name T428
Test name
Test status
Simulation time 81338199 ps
CPU time 1.14 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 215632 kb
Host smart-b382f784-d79f-493a-b5e5-6a5d5b00c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114921882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1114921882
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2117858127
Short name T269
Test name
Test status
Simulation time 26659473 ps
CPU time 1.2 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 215672 kb
Host smart-8609af8c-7e53-4fc3-bdaa-25bf10bc25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117858127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2117858127
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.330905025
Short name T518
Test name
Test status
Simulation time 78350794 ps
CPU time 2.58 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:24 PM PDT 24
Peak memory 217912 kb
Host smart-b319dd2e-f5e1-4ffc-8b23-1ba75dcfebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330905025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.330905025
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1889060717
Short name T18
Test name
Test status
Simulation time 82544977 ps
CPU time 1.27 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 214788 kb
Host smart-89476a5a-a7c8-4b17-8294-997e02e03cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889060717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1889060717
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4181280787
Short name T473
Test name
Test status
Simulation time 19718423 ps
CPU time 0.82 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 205028 kb
Host smart-1b90b36a-5d9d-4c5f-b1e0-ead920eb0398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181280787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4181280787
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.22619582
Short name T184
Test name
Test status
Simulation time 20879289 ps
CPU time 0.84 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 214588 kb
Host smart-a22e36d5-a6dd-4fe5-ab7e-955b75d70e30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.22619582
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.553526890
Short name T81
Test name
Test status
Simulation time 127603039 ps
CPU time 1.37 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:26 PM PDT 24
Peak memory 215468 kb
Host smart-07040a23-4ad3-412d-86af-bb37357d48c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553526890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.553526890
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3956755016
Short name T610
Test name
Test status
Simulation time 26005315 ps
CPU time 0.9 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 217112 kb
Host smart-7eb27763-1a6f-4422-9a92-7b6ef2224158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956755016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3956755016
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3249469839
Short name T28
Test name
Test status
Simulation time 45571643 ps
CPU time 1.29 seconds
Started Mar 10 01:37:20 PM PDT 24
Finished Mar 10 01:37:21 PM PDT 24
Peak memory 217220 kb
Host smart-56569510-b766-4ae5-9a40-46dc5894ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249469839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3249469839
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.693468363
Short name T125
Test name
Test status
Simulation time 26115237 ps
CPU time 0.96 seconds
Started Mar 10 01:37:22 PM PDT 24
Finished Mar 10 01:37:23 PM PDT 24
Peak memory 214752 kb
Host smart-87cd0193-5be5-4588-95ba-f1dafff0258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693468363 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.693468363
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2312313156
Short name T515
Test name
Test status
Simulation time 30730559 ps
CPU time 0.95 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 214420 kb
Host smart-88577906-b2a6-4d8f-9dba-6d1c1f837d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312313156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2312313156
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.4113201482
Short name T666
Test name
Test status
Simulation time 309917068 ps
CPU time 3.47 seconds
Started Mar 10 01:37:21 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 216728 kb
Host smart-4a5da206-32b9-4890-8c9f-b539d1d7301a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113201482 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4113201482
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1442142159
Short name T189
Test name
Test status
Simulation time 127530296133 ps
CPU time 989.51 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:53:53 PM PDT 24
Peak memory 222836 kb
Host smart-bd8dd7fa-4401-4dac-83eb-33d919f958b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442142159 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1442142159
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2507253890
Short name T566
Test name
Test status
Simulation time 59082118 ps
CPU time 1.28 seconds
Started Mar 10 01:39:05 PM PDT 24
Finished Mar 10 01:39:06 PM PDT 24
Peak memory 215520 kb
Host smart-ecafd7f8-475b-400a-8c45-c397c4748e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507253890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2507253890
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.272098820
Short name T760
Test name
Test status
Simulation time 47818090 ps
CPU time 1.3 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 217012 kb
Host smart-135d7e3c-1f5f-4ab7-9694-9ae9d2a05e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272098820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.272098820
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3252317769
Short name T787
Test name
Test status
Simulation time 73819323 ps
CPU time 1.38 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 217844 kb
Host smart-bce00acd-9a71-4f7d-8af7-441ebd79b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252317769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3252317769
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.757103863
Short name T297
Test name
Test status
Simulation time 45100274 ps
CPU time 1.75 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 216888 kb
Host smart-4a936960-b090-4f44-92b9-3111c40fae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757103863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.757103863
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4132920182
Short name T281
Test name
Test status
Simulation time 72906506 ps
CPU time 1.35 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 218176 kb
Host smart-035b5fbb-7d53-495f-b031-8d98c6367111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132920182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4132920182
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2059389087
Short name T366
Test name
Test status
Simulation time 43354594 ps
CPU time 1.79 seconds
Started Mar 10 01:39:07 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 216944 kb
Host smart-f938412c-889c-4cd5-955d-425b147ead9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059389087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2059389087
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2038907133
Short name T34
Test name
Test status
Simulation time 99769397 ps
CPU time 1.22 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:10 PM PDT 24
Peak memory 215732 kb
Host smart-41cb7e77-ae6f-4ea5-80e4-dff9f50e1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038907133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2038907133
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.185652261
Short name T395
Test name
Test status
Simulation time 76820636 ps
CPU time 1.36 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 216756 kb
Host smart-90a1c30b-198f-4386-aa49-79ff54165875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185652261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.185652261
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3942567923
Short name T595
Test name
Test status
Simulation time 64693582 ps
CPU time 1 seconds
Started Mar 10 01:39:08 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 214360 kb
Host smart-f1bc45e2-5c36-4efd-b765-662cceb3c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942567923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3942567923
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2610108769
Short name T694
Test name
Test status
Simulation time 83053938 ps
CPU time 1.09 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 215400 kb
Host smart-5ea7881f-f6ac-47ed-a7fb-092059421e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610108769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2610108769
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4059199184
Short name T778
Test name
Test status
Simulation time 330674016 ps
CPU time 1.3 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:07 PM PDT 24
Peak memory 214780 kb
Host smart-d016d5b3-af55-4efd-98f3-06bf58df3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059199184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4059199184
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3344999411
Short name T23
Test name
Test status
Simulation time 28033336 ps
CPU time 0.89 seconds
Started Mar 10 01:36:11 PM PDT 24
Finished Mar 10 01:36:12 PM PDT 24
Peak memory 205672 kb
Host smart-5a4ef05a-656f-4af0-9263-fc7f54c214f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344999411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3344999411
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3645289109
Short name T469
Test name
Test status
Simulation time 12459513 ps
CPU time 0.89 seconds
Started Mar 10 01:36:07 PM PDT 24
Finished Mar 10 01:36:08 PM PDT 24
Peak memory 214744 kb
Host smart-93aa0df6-b5da-44c4-a398-670fc172df06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645289109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3645289109
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3342001146
Short name T307
Test name
Test status
Simulation time 23241038 ps
CPU time 0.99 seconds
Started Mar 10 01:36:13 PM PDT 24
Finished Mar 10 01:36:14 PM PDT 24
Peak memory 215376 kb
Host smart-09555bec-025a-4bbf-bc26-261f6a7282a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342001146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3342001146
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3320232040
Short name T79
Test name
Test status
Simulation time 25226304 ps
CPU time 1 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:06 PM PDT 24
Peak memory 218396 kb
Host smart-4bcdf7ea-e897-46ae-80bf-1132d6cfd870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320232040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3320232040
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1261927758
Short name T373
Test name
Test status
Simulation time 24516936 ps
CPU time 1.21 seconds
Started Mar 10 01:36:06 PM PDT 24
Finished Mar 10 01:36:08 PM PDT 24
Peak memory 217068 kb
Host smart-32a5a2ec-216b-4dfe-90f1-74a9fa6a1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261927758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1261927758
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4041571152
Short name T810
Test name
Test status
Simulation time 22325881 ps
CPU time 1.11 seconds
Started Mar 10 01:36:07 PM PDT 24
Finished Mar 10 01:36:08 PM PDT 24
Peak memory 214664 kb
Host smart-af9f609c-4677-4f7d-b6fa-6baea474fdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041571152 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4041571152
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2517713716
Short name T592
Test name
Test status
Simulation time 125684773 ps
CPU time 0.94 seconds
Started Mar 10 01:36:05 PM PDT 24
Finished Mar 10 01:36:06 PM PDT 24
Peak memory 206188 kb
Host smart-28328bfe-60e4-4f10-8683-0be4281227c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517713716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2517713716
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.1504059154
Short name T309
Test name
Test status
Simulation time 35557937 ps
CPU time 0.9 seconds
Started Mar 10 01:36:07 PM PDT 24
Finished Mar 10 01:36:08 PM PDT 24
Peak memory 214428 kb
Host smart-ff5817ce-048c-486a-912e-03b77ddc5b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504059154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1504059154
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3740385964
Short name T452
Test name
Test status
Simulation time 506618161 ps
CPU time 4.27 seconds
Started Mar 10 01:36:06 PM PDT 24
Finished Mar 10 01:36:10 PM PDT 24
Peak memory 218440 kb
Host smart-7bd185b7-2564-4a9f-9edd-f39e763e8bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740385964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3740385964
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.513630808
Short name T191
Test name
Test status
Simulation time 104591674132 ps
CPU time 1148.66 seconds
Started Mar 10 01:36:08 PM PDT 24
Finished Mar 10 01:55:17 PM PDT 24
Peak memory 222860 kb
Host smart-97e2665e-8d35-4f7d-932e-efea0c2ffc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513630808 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.513630808
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.497840866
Short name T611
Test name
Test status
Simulation time 140220687 ps
CPU time 1.32 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 214828 kb
Host smart-17345065-2c2f-4e10-a787-175e582a8854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497840866 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.497840866
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.706044000
Short name T641
Test name
Test status
Simulation time 21872431 ps
CPU time 0.89 seconds
Started Mar 10 01:37:27 PM PDT 24
Finished Mar 10 01:37:28 PM PDT 24
Peak memory 205728 kb
Host smart-d119e6e2-4295-42a5-952f-18fc8c6a5053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706044000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.706044000
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.43692053
Short name T38
Test name
Test status
Simulation time 24342950 ps
CPU time 1.01 seconds
Started Mar 10 01:37:26 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 216656 kb
Host smart-775d6da0-642a-487c-806e-6dd4b9f76504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43692053 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_dis
able_auto_req_mode.43692053
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2535611906
Short name T86
Test name
Test status
Simulation time 91006476 ps
CPU time 1.21 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 223224 kb
Host smart-f95d02eb-3e97-463c-9863-d57a7e15d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535611906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2535611906
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1036686486
Short name T282
Test name
Test status
Simulation time 23031813 ps
CPU time 1.15 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 215744 kb
Host smart-917b8d6c-262b-4d21-af5e-b361926acac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036686486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1036686486
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3533690444
Short name T404
Test name
Test status
Simulation time 21946573 ps
CPU time 1.13 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 214536 kb
Host smart-34749be4-aeb6-4035-ab5c-431056c25cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533690444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3533690444
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3375621097
Short name T744
Test name
Test status
Simulation time 23858719 ps
CPU time 0.97 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 214424 kb
Host smart-a803da3c-5890-4acd-bb2d-bf5339ac065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375621097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3375621097
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2537141355
Short name T527
Test name
Test status
Simulation time 215474023 ps
CPU time 4.33 seconds
Started Mar 10 01:37:37 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 214344 kb
Host smart-9505fb04-b150-44b6-adfa-2d3794a91956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537141355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2537141355
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2764401255
Short name T698
Test name
Test status
Simulation time 121271438727 ps
CPU time 508.68 seconds
Started Mar 10 01:37:27 PM PDT 24
Finished Mar 10 01:45:56 PM PDT 24
Peak memory 217556 kb
Host smart-461ca462-0476-4e15-a1c0-bc8714f84de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764401255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2764401255
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3137951159
Short name T486
Test name
Test status
Simulation time 24358082 ps
CPU time 1.25 seconds
Started Mar 10 01:37:24 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 214772 kb
Host smart-3638591d-dcf5-401b-9e14-272cb3073a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137951159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3137951159
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2228647445
Short name T308
Test name
Test status
Simulation time 110327574 ps
CPU time 0.92 seconds
Started Mar 10 01:37:27 PM PDT 24
Finished Mar 10 01:37:28 PM PDT 24
Peak memory 205732 kb
Host smart-149a90f8-2f9c-4421-bc8a-4f07fb659734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228647445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2228647445
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3675543905
Short name T648
Test name
Test status
Simulation time 42629236 ps
CPU time 1.21 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:30 PM PDT 24
Peak memory 215480 kb
Host smart-11e613c8-f13d-4b4b-955a-971345214b31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675543905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3675543905
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1189514659
Short name T104
Test name
Test status
Simulation time 31283090 ps
CPU time 0.82 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 217084 kb
Host smart-b6b2cf7c-8073-4ef1-90b3-05a6217643e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189514659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1189514659
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.730755811
Short name T750
Test name
Test status
Simulation time 73245097 ps
CPU time 1.14 seconds
Started Mar 10 01:37:37 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 216580 kb
Host smart-e83db304-0011-47ac-85e8-fe9b46b99b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730755811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.730755811
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2920917177
Short name T44
Test name
Test status
Simulation time 22453907 ps
CPU time 1 seconds
Started Mar 10 01:37:23 PM PDT 24
Finished Mar 10 01:37:24 PM PDT 24
Peak memory 214772 kb
Host smart-09aa12a5-77c2-4a8c-b22d-5ce1abc413ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920917177 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2920917177
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1109709183
Short name T420
Test name
Test status
Simulation time 22963125 ps
CPU time 0.95 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 214432 kb
Host smart-4512e0dd-1e3d-4a4f-a9ad-029ea3f75501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109709183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1109709183
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3631634289
Short name T492
Test name
Test status
Simulation time 373036032 ps
CPU time 6.81 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 216856 kb
Host smart-3f1e5f0d-fcf1-4e17-b9d5-c6a7efc018e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631634289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3631634289
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3896225180
Short name T143
Test name
Test status
Simulation time 207598471843 ps
CPU time 541.32 seconds
Started Mar 10 01:37:27 PM PDT 24
Finished Mar 10 01:46:29 PM PDT 24
Peak memory 220056 kb
Host smart-2773c30b-f226-4e2c-a658-763503868ab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896225180 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3896225180
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2106249953
Short name T768
Test name
Test status
Simulation time 46436588 ps
CPU time 1.24 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:30 PM PDT 24
Peak memory 214796 kb
Host smart-5a2bb4d7-b19c-47e8-9ba2-c0c56e081b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106249953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2106249953
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2664668407
Short name T535
Test name
Test status
Simulation time 23209755 ps
CPU time 0.88 seconds
Started Mar 10 01:37:30 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 205292 kb
Host smart-4ff590c8-4b7a-4a06-b859-eb2281d473a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664668407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2664668407
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2408000368
Short name T107
Test name
Test status
Simulation time 14061130 ps
CPU time 0.94 seconds
Started Mar 10 01:37:31 PM PDT 24
Finished Mar 10 01:37:33 PM PDT 24
Peak memory 215096 kb
Host smart-ba7d8f31-3280-412d-bf48-cb96b28843d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408000368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2408000368
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.794039851
Short name T66
Test name
Test status
Simulation time 40013571 ps
CPU time 1.26 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 215364 kb
Host smart-d1310ee1-a6ac-4a71-8529-d84e099f7ea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794039851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.794039851
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.832021072
Short name T789
Test name
Test status
Simulation time 19868067 ps
CPU time 1 seconds
Started Mar 10 01:37:32 PM PDT 24
Finished Mar 10 01:37:33 PM PDT 24
Peak memory 217364 kb
Host smart-9a86bd79-73d9-44a2-8d14-4e1fd6f8e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832021072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.832021072
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.735125666
Short name T295
Test name
Test status
Simulation time 77534301 ps
CPU time 2.73 seconds
Started Mar 10 01:37:26 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 217008 kb
Host smart-659852dc-7f79-4596-9e9b-81fe6e8a00a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735125666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.735125666
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2113800825
Short name T579
Test name
Test status
Simulation time 29729556 ps
CPU time 1.02 seconds
Started Mar 10 01:37:25 PM PDT 24
Finished Mar 10 01:37:26 PM PDT 24
Peak memory 222304 kb
Host smart-e20774c5-9de9-4d3a-ae9c-addc796137fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113800825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2113800825
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.562921669
Short name T598
Test name
Test status
Simulation time 15788167 ps
CPU time 0.96 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:30 PM PDT 24
Peak memory 214408 kb
Host smart-6549901a-9ad3-4d3d-b55c-0036b5f7f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562921669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.562921669
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.951531546
Short name T154
Test name
Test status
Simulation time 78207553 ps
CPU time 1.36 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:30 PM PDT 24
Peak memory 214396 kb
Host smart-0ebc9439-4eb8-48e5-842d-22babfabc15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951531546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.951531546
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert_test.3331618640
Short name T332
Test name
Test status
Simulation time 38237917 ps
CPU time 0.84 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:37:41 PM PDT 24
Peak memory 205560 kb
Host smart-c7bb61e5-c215-4db1-a77e-fca68f516ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331618640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3331618640
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2986796711
Short name T165
Test name
Test status
Simulation time 30522365 ps
CPU time 1.08 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 215476 kb
Host smart-779938d1-cc45-495b-a648-63be2301f5d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986796711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2986796711
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3810429014
Short name T48
Test name
Test status
Simulation time 36658560 ps
CPU time 1.05 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 222188 kb
Host smart-653bfe68-6c95-434c-bb49-9abd2ed2890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810429014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3810429014
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2920869272
Short name T836
Test name
Test status
Simulation time 87350382 ps
CPU time 1.54 seconds
Started Mar 10 01:37:32 PM PDT 24
Finished Mar 10 01:37:34 PM PDT 24
Peak memory 217224 kb
Host smart-7b0185a3-9da6-48eb-b251-1def8dbeb2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920869272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2920869272
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3903166083
Short name T129
Test name
Test status
Simulation time 43265194 ps
CPU time 0.84 seconds
Started Mar 10 01:37:28 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 214664 kb
Host smart-1f2f4c2c-f63b-444e-aa47-888f71ee323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903166083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3903166083
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3930842461
Short name T381
Test name
Test status
Simulation time 28580799 ps
CPU time 0.89 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:30 PM PDT 24
Peak memory 214424 kb
Host smart-136e7cdb-ed81-4d22-947c-26b21041094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930842461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3930842461
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3945661724
Short name T536
Test name
Test status
Simulation time 753130757 ps
CPU time 1.97 seconds
Started Mar 10 01:37:29 PM PDT 24
Finished Mar 10 01:37:31 PM PDT 24
Peak memory 218196 kb
Host smart-3eb8a241-fdcb-4225-858e-321b7b976d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945661724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3945661724
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3332356298
Short name T571
Test name
Test status
Simulation time 61512874337 ps
CPU time 802.65 seconds
Started Mar 10 01:37:30 PM PDT 24
Finished Mar 10 01:50:53 PM PDT 24
Peak memory 220380 kb
Host smart-95547be0-20da-4c82-ac13-3145c0731b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332356298 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3332356298
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.852253743
Short name T100
Test name
Test status
Simulation time 90991243 ps
CPU time 1.18 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 214744 kb
Host smart-674f36bf-e9ed-4e86-9e79-5385967260f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852253743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.852253743
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1642802515
Short name T315
Test name
Test status
Simulation time 28370447 ps
CPU time 0.91 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 206096 kb
Host smart-cb77fbf3-3f22-42b4-903b-06978aded141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642802515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1642802515
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2753410735
Short name T603
Test name
Test status
Simulation time 26779468 ps
CPU time 0.87 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 214936 kb
Host smart-a57c670c-8618-4d4f-ac8e-54a3fa1c3393
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753410735 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2753410735
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3993852114
Short name T77
Test name
Test status
Simulation time 91913508 ps
CPU time 1.13 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:37 PM PDT 24
Peak memory 215336 kb
Host smart-057020d0-3d71-421e-9071-3a78ded78b4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993852114 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3993852114
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.188604239
Short name T537
Test name
Test status
Simulation time 61158562 ps
CPU time 0.85 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 216704 kb
Host smart-88d343cd-5647-44d0-a7e8-c1a2d6e5a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188604239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.188604239
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.790806045
Short name T531
Test name
Test status
Simulation time 174258486 ps
CPU time 1.19 seconds
Started Mar 10 01:37:35 PM PDT 24
Finished Mar 10 01:37:36 PM PDT 24
Peak memory 215856 kb
Host smart-893ca865-ef8f-43df-aebf-c021669e862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790806045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.790806045
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.833560058
Short name T804
Test name
Test status
Simulation time 28291174 ps
CPU time 0.98 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:37 PM PDT 24
Peak memory 214748 kb
Host smart-dd6ad8d3-f473-4fc8-8d8d-f2883f080374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833560058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.833560058
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3538244675
Short name T544
Test name
Test status
Simulation time 123570602 ps
CPU time 0.86 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:45 PM PDT 24
Peak memory 214304 kb
Host smart-cf6aaa18-6fca-4c0d-b966-e5ab5e30fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538244675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3538244675
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.883121331
Short name T729
Test name
Test status
Simulation time 615578920 ps
CPU time 2.64 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 214316 kb
Host smart-d5058768-071f-48b7-bcab-65a4a558390c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883121331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.883121331
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2780927670
Short name T192
Test name
Test status
Simulation time 146216930414 ps
CPU time 1609.52 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 02:04:24 PM PDT 24
Peak memory 223088 kb
Host smart-e2e0a656-5fb9-44ca-90bb-bb39c19f47bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780927670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2780927670
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3141493626
Short name T259
Test name
Test status
Simulation time 30554022 ps
CPU time 1.3 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 214468 kb
Host smart-5dfe72a8-5729-4df5-a89e-492c0a50b22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141493626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3141493626
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.691178662
Short name T833
Test name
Test status
Simulation time 76464645 ps
CPU time 0.97 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:37 PM PDT 24
Peak memory 206108 kb
Host smart-ce73df32-c799-47dd-9d54-55c6532ce38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691178662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.691178662
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.688351976
Short name T156
Test name
Test status
Simulation time 19601693 ps
CPU time 0.86 seconds
Started Mar 10 01:37:35 PM PDT 24
Finished Mar 10 01:37:36 PM PDT 24
Peak memory 214884 kb
Host smart-8eb23ec2-4f1a-4c69-862d-c93b0ac7f5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688351976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.688351976
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3302778515
Short name T302
Test name
Test status
Simulation time 20469373 ps
CPU time 0.99 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:37 PM PDT 24
Peak memory 216848 kb
Host smart-415a257b-f6a2-4c15-91ad-bbe10b487db1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302778515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3302778515
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1784114937
Short name T74
Test name
Test status
Simulation time 19818377 ps
CPU time 1.06 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:37:41 PM PDT 24
Peak memory 216984 kb
Host smart-fb406dbf-dd92-46aa-aea4-fe63ca5fa873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784114937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1784114937
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1794606800
Short name T375
Test name
Test status
Simulation time 262128071 ps
CPU time 3.41 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 215980 kb
Host smart-25dc515a-264e-4b5f-9ef6-9cb32940f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794606800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1794606800
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.377972379
Short name T133
Test name
Test status
Simulation time 21292533 ps
CPU time 1.05 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 214740 kb
Host smart-7e1f437f-934a-4e82-aeea-dfd4767e8f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377972379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.377972379
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1533126091
Short name T318
Test name
Test status
Simulation time 19876007 ps
CPU time 0.91 seconds
Started Mar 10 01:37:33 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 214420 kb
Host smart-be52ea8a-7ae9-42b2-b0b1-cc0570b5a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533126091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1533126091
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3110141984
Short name T745
Test name
Test status
Simulation time 468352736 ps
CPU time 4.73 seconds
Started Mar 10 01:37:35 PM PDT 24
Finished Mar 10 01:37:40 PM PDT 24
Peak memory 214404 kb
Host smart-f1e1b01c-dfd9-46c9-ad3b-50fd86e22a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110141984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3110141984
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2198504842
Short name T553
Test name
Test status
Simulation time 70590652476 ps
CPU time 404.68 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:44:24 PM PDT 24
Peak memory 222712 kb
Host smart-2dfb0536-1dab-4db2-9ddc-c3d2fcd3e0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198504842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2198504842
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1393474798
Short name T702
Test name
Test status
Simulation time 45250928 ps
CPU time 1.13 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 214712 kb
Host smart-bac1f687-deee-4ae4-bc8a-ac5c9c7eb657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393474798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1393474798
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3017350168
Short name T816
Test name
Test status
Simulation time 22483373 ps
CPU time 0.89 seconds
Started Mar 10 01:37:39 PM PDT 24
Finished Mar 10 01:37:40 PM PDT 24
Peak memory 206084 kb
Host smart-1d7e6666-261a-4bd4-af25-ce562ad1c1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017350168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3017350168
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.179448255
Short name T87
Test name
Test status
Simulation time 42890969 ps
CPU time 0.86 seconds
Started Mar 10 01:37:41 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 214664 kb
Host smart-7a04d337-1368-4d7f-a273-39794d470c0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179448255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.179448255
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2624848332
Short name T802
Test name
Test status
Simulation time 73966774 ps
CPU time 1 seconds
Started Mar 10 01:37:41 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 215408 kb
Host smart-b278c045-4bdb-40f8-a2c7-df54e89a659f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624848332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2624848332
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3559549295
Short name T436
Test name
Test status
Simulation time 35111402 ps
CPU time 1.02 seconds
Started Mar 10 01:37:41 PM PDT 24
Finished Mar 10 01:37:43 PM PDT 24
Peak memory 222328 kb
Host smart-e2a2f972-cf8d-4e7e-979d-08410d945519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559549295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3559549295
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.307052260
Short name T388
Test name
Test status
Simulation time 44595708 ps
CPU time 1.3 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 216996 kb
Host smart-a531d593-8bc9-4515-ba38-67d39f5c028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307052260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.307052260
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2203090470
Short name T333
Test name
Test status
Simulation time 21665436 ps
CPU time 1.07 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 214568 kb
Host smart-c6d098b9-690d-4d81-8f9c-2e83ac523fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203090470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2203090470
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.669015296
Short name T662
Test name
Test status
Simulation time 29003340 ps
CPU time 0.9 seconds
Started Mar 10 01:37:36 PM PDT 24
Finished Mar 10 01:37:37 PM PDT 24
Peak memory 214420 kb
Host smart-a81a7f80-1c59-4f91-bc9b-80d1cf0b3af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669015296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.669015296
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.857909397
Short name T305
Test name
Test status
Simulation time 698477952 ps
CPU time 3.99 seconds
Started Mar 10 01:37:37 PM PDT 24
Finished Mar 10 01:37:41 PM PDT 24
Peak memory 215556 kb
Host smart-76bf4153-c555-4e83-9c06-717908d56224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857909397 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.857909397
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1015276555
Short name T26
Test name
Test status
Simulation time 300475737242 ps
CPU time 1904.84 seconds
Started Mar 10 01:37:34 PM PDT 24
Finished Mar 10 02:09:19 PM PDT 24
Peak memory 223108 kb
Host smart-564c0374-2ad0-4227-88bb-b6fc598c097d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015276555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1015276555
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3847046740
Short name T149
Test name
Test status
Simulation time 90532864 ps
CPU time 1.25 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 214820 kb
Host smart-9a5010c9-bdb9-40b9-9adc-2b8f6a6823dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847046740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3847046740
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1141549511
Short name T632
Test name
Test status
Simulation time 21221931 ps
CPU time 0.82 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 205008 kb
Host smart-1cbb954e-cb7b-44a8-b9e6-443c3a77249e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141549511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1141549511
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1212563533
Short name T109
Test name
Test status
Simulation time 22360458 ps
CPU time 0.9 seconds
Started Mar 10 01:37:42 PM PDT 24
Finished Mar 10 01:37:43 PM PDT 24
Peak memory 214896 kb
Host smart-85639fe1-42a9-45ed-8b7e-c417be837dc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212563533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1212563533
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3790294175
Short name T72
Test name
Test status
Simulation time 99001915 ps
CPU time 1.04 seconds
Started Mar 10 01:37:39 PM PDT 24
Finished Mar 10 01:37:40 PM PDT 24
Peak memory 216816 kb
Host smart-41a0f761-4f55-4056-952a-abf4a8d6b00d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790294175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3790294175
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2174535887
Short name T633
Test name
Test status
Simulation time 18915594 ps
CPU time 1.04 seconds
Started Mar 10 01:37:39 PM PDT 24
Finished Mar 10 01:37:40 PM PDT 24
Peak memory 216928 kb
Host smart-5b9cd756-bcd1-4411-8898-61b8011843c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174535887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2174535887
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1281727562
Short name T286
Test name
Test status
Simulation time 45605730 ps
CPU time 1.81 seconds
Started Mar 10 01:37:41 PM PDT 24
Finished Mar 10 01:37:43 PM PDT 24
Peak memory 217032 kb
Host smart-e4603415-e44d-4dd6-b355-8ea4ba61d2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281727562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1281727562
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3302177767
Short name T539
Test name
Test status
Simulation time 29962830 ps
CPU time 0.94 seconds
Started Mar 10 01:37:38 PM PDT 24
Finished Mar 10 01:37:39 PM PDT 24
Peak memory 214536 kb
Host smart-0f9fa17c-7ebe-497f-8dc5-0a25bbf68723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302177767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3302177767
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3162833446
Short name T301
Test name
Test status
Simulation time 21462035 ps
CPU time 0.99 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:37:41 PM PDT 24
Peak memory 206224 kb
Host smart-d5c2f7d8-3d16-4bd5-8fb4-de8ed3ba35f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162833446 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3162833446
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2453541030
Short name T135
Test name
Test status
Simulation time 24381218 ps
CPU time 1.12 seconds
Started Mar 10 01:37:42 PM PDT 24
Finished Mar 10 01:37:43 PM PDT 24
Peak memory 214460 kb
Host smart-cd49488d-f159-45dd-992b-128d7ef4a853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453541030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2453541030
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2978494471
Short name T620
Test name
Test status
Simulation time 309570697527 ps
CPU time 520.19 seconds
Started Mar 10 01:37:43 PM PDT 24
Finished Mar 10 01:46:23 PM PDT 24
Peak memory 222856 kb
Host smart-cea72955-5664-4759-ac9c-e3935127608b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978494471 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2978494471
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3307086459
Short name T693
Test name
Test status
Simulation time 33664047 ps
CPU time 1.34 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 214748 kb
Host smart-43d0388d-e610-4462-a354-c71076665b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307086459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3307086459
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1930691900
Short name T660
Test name
Test status
Simulation time 22286907 ps
CPU time 0.81 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 204948 kb
Host smart-bb43c0b7-d33d-42ad-840f-b45d8b90626f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930691900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1930691900
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1213259201
Short name T627
Test name
Test status
Simulation time 18200710 ps
CPU time 0.87 seconds
Started Mar 10 01:37:43 PM PDT 24
Finished Mar 10 01:37:44 PM PDT 24
Peak memory 214876 kb
Host smart-b05f0c3a-f1bb-4229-8704-5af50a592c9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213259201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1213259201
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.33959980
Short name T397
Test name
Test status
Simulation time 148543029 ps
CPU time 1.25 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:45 PM PDT 24
Peak memory 215544 kb
Host smart-a94aa855-cdfc-40dc-8d75-0e92edc335ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33959980 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_dis
able_auto_req_mode.33959980
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4280424829
Short name T64
Test name
Test status
Simulation time 35817130 ps
CPU time 1.07 seconds
Started Mar 10 01:37:46 PM PDT 24
Finished Mar 10 01:37:48 PM PDT 24
Peak memory 219260 kb
Host smart-3125da9a-2b12-4a4b-a269-9d96657ca522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280424829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4280424829
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3824076286
Short name T390
Test name
Test status
Simulation time 36226254 ps
CPU time 1.2 seconds
Started Mar 10 01:37:40 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 215580 kb
Host smart-b711d5db-5e74-4448-aef5-755d0d7dfbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824076286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3824076286
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2435164509
Short name T630
Test name
Test status
Simulation time 19836569 ps
CPU time 1.09 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 214804 kb
Host smart-2c4f1236-99f8-4807-bb1d-9324b23a44e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435164509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2435164509
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1856227759
Short name T543
Test name
Test status
Simulation time 17381368 ps
CPU time 0.98 seconds
Started Mar 10 01:37:39 PM PDT 24
Finished Mar 10 01:37:40 PM PDT 24
Peak memory 214448 kb
Host smart-a6441487-3813-40c7-a360-1a341582ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856227759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1856227759
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2327459343
Short name T52
Test name
Test status
Simulation time 426623244 ps
CPU time 2.75 seconds
Started Mar 10 01:37:39 PM PDT 24
Finished Mar 10 01:37:42 PM PDT 24
Peak memory 215304 kb
Host smart-8a8bc151-9f43-40b0-a8f5-5c02284d49df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327459343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2327459343
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.2277475375
Short name T146
Test name
Test status
Simulation time 249126795 ps
CPU time 1.31 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:47 PM PDT 24
Peak memory 214780 kb
Host smart-8d2b0545-b063-49b2-b972-006b62c91fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277475375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2277475375
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.794115998
Short name T306
Test name
Test status
Simulation time 25166717 ps
CPU time 1.05 seconds
Started Mar 10 01:37:47 PM PDT 24
Finished Mar 10 01:37:48 PM PDT 24
Peak memory 206108 kb
Host smart-832da2c4-e348-4b97-888c-dc7ca10dfa53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794115998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.794115998
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1445622078
Short name T173
Test name
Test status
Simulation time 129828681 ps
CPU time 1.24 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:53 PM PDT 24
Peak memory 215392 kb
Host smart-acb90e9d-3648-4b45-bcdc-5d830a543db1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445622078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1445622078
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4206647081
Short name T171
Test name
Test status
Simulation time 35285105 ps
CPU time 0.89 seconds
Started Mar 10 01:37:46 PM PDT 24
Finished Mar 10 01:37:47 PM PDT 24
Peak memory 217196 kb
Host smart-ec535be0-6da7-451e-8f43-b85506aaf00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206647081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4206647081
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.372092390
Short name T574
Test name
Test status
Simulation time 44456301 ps
CPU time 1.24 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 216668 kb
Host smart-034639c8-a9fe-4683-a781-f2756ca75a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372092390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.372092390
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.666356483
Short name T128
Test name
Test status
Simulation time 21332538 ps
CPU time 1.13 seconds
Started Mar 10 01:37:43 PM PDT 24
Finished Mar 10 01:37:44 PM PDT 24
Peak memory 214704 kb
Host smart-1b45459e-f332-4077-ab05-b216e2dc4715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666356483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.666356483
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1653523664
Short name T761
Test name
Test status
Simulation time 78522271 ps
CPU time 0.92 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 214328 kb
Host smart-516d247d-13de-4a33-9c50-af2825f62205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653523664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1653523664
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1404009840
Short name T679
Test name
Test status
Simulation time 643364295 ps
CPU time 4.63 seconds
Started Mar 10 01:37:47 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 218372 kb
Host smart-efa69266-b40a-405f-887b-df28cc1005ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404009840 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1404009840
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.798369001
Short name T607
Test name
Test status
Simulation time 66360348528 ps
CPU time 1421.03 seconds
Started Mar 10 01:37:46 PM PDT 24
Finished Mar 10 02:01:27 PM PDT 24
Peak memory 221156 kb
Host smart-05e0d746-ab4b-463a-807f-5ef1dbd24d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798369001 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.798369001
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3104282081
Short name T117
Test name
Test status
Simulation time 26780417 ps
CPU time 1.3 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 214768 kb
Host smart-77c964f0-cb7f-4fff-808d-334cb6f51b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104282081 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3104282081
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2222098201
Short name T42
Test name
Test status
Simulation time 27353147 ps
CPU time 0.93 seconds
Started Mar 10 01:36:17 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 206072 kb
Host smart-b2187834-d2d4-475d-b2c8-c6feef618ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222098201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2222098201
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_err.3025610250
Short name T31
Test name
Test status
Simulation time 18583187 ps
CPU time 1.04 seconds
Started Mar 10 01:36:15 PM PDT 24
Finished Mar 10 01:36:16 PM PDT 24
Peak memory 217088 kb
Host smart-57a99fdc-5db6-4ea8-a8fc-8cb76a26e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025610250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3025610250
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.877400582
Short name T798
Test name
Test status
Simulation time 149869660 ps
CPU time 2.89 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:17 PM PDT 24
Peak memory 217152 kb
Host smart-1d270920-3803-4eed-a7b1-1f585995064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877400582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.877400582
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.277656489
Short name T22
Test name
Test status
Simulation time 218179977 ps
CPU time 3.66 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 232504 kb
Host smart-8efa8f1e-8c8e-40f4-9728-44d1cadeda7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277656489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.277656489
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2477493420
Short name T377
Test name
Test status
Simulation time 27913321 ps
CPU time 0.93 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 214408 kb
Host smart-70488cb8-c791-4b00-9cc3-248e5087c5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477493420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2477493420
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.637734711
Short name T322
Test name
Test status
Simulation time 467223357 ps
CPU time 5.3 seconds
Started Mar 10 01:36:14 PM PDT 24
Finished Mar 10 01:36:20 PM PDT 24
Peak memory 215460 kb
Host smart-9eefeaa9-3430-4507-8f70-e49a0fe68a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637734711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.637734711
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1615058721
Short name T777
Test name
Test status
Simulation time 78855967667 ps
CPU time 1830.17 seconds
Started Mar 10 01:36:20 PM PDT 24
Finished Mar 10 02:06:50 PM PDT 24
Peak memory 226288 kb
Host smart-e9d2a751-7730-44b7-a4cf-c945946654b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615058721 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1615058721
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3679999477
Short name T250
Test name
Test status
Simulation time 42201272 ps
CPU time 1.11 seconds
Started Mar 10 01:37:46 PM PDT 24
Finished Mar 10 01:37:47 PM PDT 24
Peak memory 214756 kb
Host smart-da6641f9-d5ea-432a-b6d5-6c02c21fa8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679999477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3679999477
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1582104619
Short name T441
Test name
Test status
Simulation time 19075185 ps
CPU time 0.85 seconds
Started Mar 10 01:37:48 PM PDT 24
Finished Mar 10 01:37:49 PM PDT 24
Peak memory 206020 kb
Host smart-0c293976-9df3-4ecc-9888-c240314ebefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582104619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1582104619
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1023956105
Short name T398
Test name
Test status
Simulation time 13821878 ps
CPU time 0.93 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:45 PM PDT 24
Peak memory 214980 kb
Host smart-12b650a1-9a2b-4e44-a866-8ce65f98fbd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023956105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1023956105
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1262834319
Short name T83
Test name
Test status
Simulation time 45772931 ps
CPU time 1.6 seconds
Started Mar 10 01:37:44 PM PDT 24
Finished Mar 10 01:37:46 PM PDT 24
Peak memory 215472 kb
Host smart-0bac906a-d0cc-4f6f-910c-6303e2f233d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262834319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1262834319
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1313046223
Short name T811
Test name
Test status
Simulation time 39794526 ps
CPU time 0.86 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 217096 kb
Host smart-e56dcbd0-216c-4e28-807a-5c611f1a1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313046223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1313046223
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.922909456
Short name T625
Test name
Test status
Simulation time 135974120 ps
CPU time 1.22 seconds
Started Mar 10 01:37:48 PM PDT 24
Finished Mar 10 01:37:49 PM PDT 24
Peak memory 215792 kb
Host smart-88b84698-7ffb-464b-a85f-132016d798e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922909456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.922909456
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4075406565
Short name T569
Test name
Test status
Simulation time 47514002 ps
CPU time 0.94 seconds
Started Mar 10 01:37:47 PM PDT 24
Finished Mar 10 01:37:48 PM PDT 24
Peak memory 214484 kb
Host smart-a267d840-38c1-4cee-aa94-b47a3b8d12b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075406565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4075406565
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2653113514
Short name T376
Test name
Test status
Simulation time 69409853 ps
CPU time 0.87 seconds
Started Mar 10 01:37:49 PM PDT 24
Finished Mar 10 01:37:50 PM PDT 24
Peak memory 214324 kb
Host smart-cddf83c2-b3ff-4adb-8f30-6ebba90d16c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653113514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2653113514
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1495208504
Short name T508
Test name
Test status
Simulation time 298196898 ps
CPU time 2.32 seconds
Started Mar 10 01:37:45 PM PDT 24
Finished Mar 10 01:37:48 PM PDT 24
Peak memory 214380 kb
Host smart-bb80c596-0749-4803-bd98-c3274406d802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495208504 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1495208504
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.246693250
Short name T506
Test name
Test status
Simulation time 259404803518 ps
CPU time 677.3 seconds
Started Mar 10 01:37:47 PM PDT 24
Finished Mar 10 01:49:04 PM PDT 24
Peak memory 222736 kb
Host smart-a1820bad-40b5-42ce-948a-50306f53082e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246693250 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.246693250
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.787553336
Short name T621
Test name
Test status
Simulation time 49411947 ps
CPU time 1.27 seconds
Started Mar 10 01:37:52 PM PDT 24
Finished Mar 10 01:37:53 PM PDT 24
Peak memory 214768 kb
Host smart-db1c3606-239b-4a50-ab66-3e83f8959ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787553336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.787553336
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3499428871
Short name T773
Test name
Test status
Simulation time 22433933 ps
CPU time 0.84 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 204992 kb
Host smart-e6074f04-fb25-4db2-abce-2475a3f75d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499428871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3499428871
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1772476464
Short name T153
Test name
Test status
Simulation time 111564437 ps
CPU time 0.83 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 214912 kb
Host smart-78bfb2d8-b682-40bc-937f-a07f08fe6537
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772476464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1772476464
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1949879324
Short name T447
Test name
Test status
Simulation time 25141129 ps
CPU time 1.1 seconds
Started Mar 10 01:37:52 PM PDT 24
Finished Mar 10 01:37:53 PM PDT 24
Peak memory 216696 kb
Host smart-5b12a503-a56f-4198-aca0-f6046411bb46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949879324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1949879324
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2148670875
Short name T669
Test name
Test status
Simulation time 21913333 ps
CPU time 1.06 seconds
Started Mar 10 01:37:54 PM PDT 24
Finished Mar 10 01:37:55 PM PDT 24
Peak memory 222204 kb
Host smart-5681de13-4baf-4317-a63f-8ade45f95697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148670875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2148670875
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3894638096
Short name T271
Test name
Test status
Simulation time 47478468 ps
CPU time 1.84 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:53 PM PDT 24
Peak memory 216720 kb
Host smart-24f451ae-f5ec-4951-88fd-4c27ec1218f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894638096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3894638096
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.535411949
Short name T394
Test name
Test status
Simulation time 85935823 ps
CPU time 0.85 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 214472 kb
Host smart-b91790ff-a317-43ed-b6c9-3c2b2a36d128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535411949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.535411949
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.202708033
Short name T444
Test name
Test status
Simulation time 50311173 ps
CPU time 0.95 seconds
Started Mar 10 01:37:52 PM PDT 24
Finished Mar 10 01:37:53 PM PDT 24
Peak memory 214388 kb
Host smart-c373b61b-c2cd-48e9-bc7d-3c1adb2199fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202708033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.202708033
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2636730776
Short name T672
Test name
Test status
Simulation time 851584781 ps
CPU time 5.41 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:56 PM PDT 24
Peak memory 218428 kb
Host smart-3b057709-62ba-4f08-982e-c9d7440116a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636730776 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2636730776
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1972519582
Short name T137
Test name
Test status
Simulation time 28614462791 ps
CPU time 756.67 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:50:27 PM PDT 24
Peak memory 216752 kb
Host smart-a979e05f-e782-4058-91a3-db73a2cdf5b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972519582 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1972519582
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2723051227
Short name T95
Test name
Test status
Simulation time 73655103 ps
CPU time 1.16 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 214800 kb
Host smart-4a55e36b-40c8-46dd-abf5-3f04ea076de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723051227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2723051227
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1961230125
Short name T327
Test name
Test status
Simulation time 21252619 ps
CPU time 0.84 seconds
Started Mar 10 01:37:54 PM PDT 24
Finished Mar 10 01:37:55 PM PDT 24
Peak memory 205764 kb
Host smart-551c349f-ccb7-43d0-802b-c7def262c8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961230125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1961230125
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.325174715
Short name T654
Test name
Test status
Simulation time 41910264 ps
CPU time 0.9 seconds
Started Mar 10 01:37:51 PM PDT 24
Finished Mar 10 01:37:52 PM PDT 24
Peak memory 214624 kb
Host smart-fa27330c-b115-4750-8541-e0bd538b89f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325174715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.325174715
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.964484488
Short name T794
Test name
Test status
Simulation time 33868600 ps
CPU time 1.3 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:57 PM PDT 24
Peak memory 215572 kb
Host smart-622d5051-fa6e-458e-9c61-ff26ee4c1225
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964484488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.964484488
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4016681131
Short name T159
Test name
Test status
Simulation time 33533857 ps
CPU time 0.98 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 222172 kb
Host smart-0df76255-9847-4254-b95f-d4125456e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016681131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4016681131
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.638876206
Short name T139
Test name
Test status
Simulation time 36729007 ps
CPU time 1.26 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 215688 kb
Host smart-4266847e-973c-4fdb-8d14-79f6c38f8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638876206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.638876206
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.214713124
Short name T656
Test name
Test status
Simulation time 31406341 ps
CPU time 0.9 seconds
Started Mar 10 01:37:48 PM PDT 24
Finished Mar 10 01:37:49 PM PDT 24
Peak memory 214524 kb
Host smart-81147670-4bca-4e7b-9622-1c549c58ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214713124 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.214713124
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.745109858
Short name T730
Test name
Test status
Simulation time 25826915 ps
CPU time 0.93 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 214400 kb
Host smart-660b2b18-49cf-491d-a6d5-5988e0cd7a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745109858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.745109858
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3517181283
Short name T263
Test name
Test status
Simulation time 58788750 ps
CPU time 1.21 seconds
Started Mar 10 01:37:50 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 215732 kb
Host smart-bfc24a60-1d52-44e8-a7ea-ea3b7fa3f8df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517181283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3517181283
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2518015579
Short name T841
Test name
Test status
Simulation time 169665321138 ps
CPU time 888.36 seconds
Started Mar 10 01:37:53 PM PDT 24
Finished Mar 10 01:52:41 PM PDT 24
Peak memory 219852 kb
Host smart-50ef8b1c-6493-4d03-bd11-30dd93355baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518015579 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2518015579
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.108597466
Short name T720
Test name
Test status
Simulation time 82201156 ps
CPU time 1.19 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:57 PM PDT 24
Peak memory 214860 kb
Host smart-a7abb6e5-f51d-4daf-8292-2fa801bc7ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108597466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.108597466
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3362069926
Short name T329
Test name
Test status
Simulation time 30884181 ps
CPU time 0.94 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 205708 kb
Host smart-c139ff4e-7bb6-4804-9b6b-6d3a698f8280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362069926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3362069926
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4237147544
Short name T113
Test name
Test status
Simulation time 39793128 ps
CPU time 0.85 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 214868 kb
Host smart-908c5081-e580-433e-98a1-6979eee5dcfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237147544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4237147544
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4045354300
Short name T551
Test name
Test status
Simulation time 227113319 ps
CPU time 1.09 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 216696 kb
Host smart-d1375258-cc6c-4eec-97b5-b10991988595
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045354300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4045354300
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.370782832
Short name T162
Test name
Test status
Simulation time 26470108 ps
CPU time 1.23 seconds
Started Mar 10 01:37:56 PM PDT 24
Finished Mar 10 01:37:57 PM PDT 24
Peak memory 215932 kb
Host smart-7feba2d8-de50-44b7-88fd-9b442b1bf952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370782832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.370782832
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_intr.4214173559
Short name T655
Test name
Test status
Simulation time 31478766 ps
CPU time 0.95 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:56 PM PDT 24
Peak memory 214700 kb
Host smart-bdd873df-6218-45f9-a9cd-254d605a0b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214173559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4214173559
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.938157045
Short name T687
Test name
Test status
Simulation time 14528424 ps
CPU time 1.02 seconds
Started Mar 10 01:37:54 PM PDT 24
Finished Mar 10 01:37:55 PM PDT 24
Peak memory 214408 kb
Host smart-6aedd391-ff13-496d-b377-988115592696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938157045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.938157045
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.46535614
Short name T367
Test name
Test status
Simulation time 144602594 ps
CPU time 1.36 seconds
Started Mar 10 01:37:56 PM PDT 24
Finished Mar 10 01:37:58 PM PDT 24
Peak memory 215712 kb
Host smart-d48a4188-7cdd-4f7c-96f5-af8726ad7bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46535614 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.46535614
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.318151708
Short name T193
Test name
Test status
Simulation time 35132062385 ps
CPU time 435.2 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:45:20 PM PDT 24
Peak memory 217828 kb
Host smart-65328a14-e84e-424d-8e78-5e45605a9d4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318151708 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.318151708
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2859614940
Short name T257
Test name
Test status
Simulation time 48753864 ps
CPU time 1.33 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 214776 kb
Host smart-54a69f8d-afa4-49a3-8ebf-cbf59bad626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859614940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2859614940
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.793492092
Short name T572
Test name
Test status
Simulation time 30403531 ps
CPU time 0.88 seconds
Started Mar 10 01:38:12 PM PDT 24
Finished Mar 10 01:38:13 PM PDT 24
Peak memory 205948 kb
Host smart-d5c00202-ba2c-4910-b3c8-10dc30444d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793492092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.793492092
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_err.2075126986
Short name T70
Test name
Test status
Simulation time 74394221 ps
CPU time 1.09 seconds
Started Mar 10 01:37:57 PM PDT 24
Finished Mar 10 01:37:58 PM PDT 24
Peak memory 228972 kb
Host smart-7b7f4adc-a4c7-4ceb-95cf-6db843a52824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075126986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2075126986
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.154349846
Short name T718
Test name
Test status
Simulation time 62020026 ps
CPU time 1.07 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:57 PM PDT 24
Peak memory 217012 kb
Host smart-ccf358fd-c09b-45b1-ab97-e3db45f643af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154349846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.154349846
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.115552170
Short name T470
Test name
Test status
Simulation time 29724585 ps
CPU time 0.92 seconds
Started Mar 10 01:37:57 PM PDT 24
Finished Mar 10 01:37:58 PM PDT 24
Peak memory 214768 kb
Host smart-c3c727de-b8d1-4b48-8e37-6e5bec3baf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115552170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.115552170
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2748393537
Short name T823
Test name
Test status
Simulation time 54266076 ps
CPU time 0.97 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:56 PM PDT 24
Peak memory 214392 kb
Host smart-9c40430b-f97b-4f67-b8d3-a196274d22e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748393537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2748393537
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2961998995
Short name T808
Test name
Test status
Simulation time 784637562 ps
CPU time 3.57 seconds
Started Mar 10 01:37:55 PM PDT 24
Finished Mar 10 01:37:59 PM PDT 24
Peak memory 218384 kb
Host smart-22514210-09cf-4b80-ba34-e6ac8da18a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961998995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2961998995
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1341967369
Short name T186
Test name
Test status
Simulation time 523346314859 ps
CPU time 1053.44 seconds
Started Mar 10 01:37:57 PM PDT 24
Finished Mar 10 01:55:31 PM PDT 24
Peak memory 226660 kb
Host smart-a6f6c412-0442-4001-8321-449abf79abdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341967369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1341967369
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3919593939
Short name T150
Test name
Test status
Simulation time 30419490 ps
CPU time 1.34 seconds
Started Mar 10 01:37:54 PM PDT 24
Finished Mar 10 01:37:56 PM PDT 24
Peak memory 214796 kb
Host smart-15338e24-71b6-4e90-b77d-8c2f81e52a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919593939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3919593939
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3241489487
Short name T316
Test name
Test status
Simulation time 78377552 ps
CPU time 1.8 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:02 PM PDT 24
Peak memory 206088 kb
Host smart-ccaecd21-262c-4aef-b442-f2ae005b73c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241489487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3241489487
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.474234376
Short name T170
Test name
Test status
Simulation time 21723173 ps
CPU time 0.92 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 214864 kb
Host smart-76da7cba-120c-46b8-8a15-4de5822ef3a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474234376 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.474234376
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3163763162
Short name T450
Test name
Test status
Simulation time 21817108 ps
CPU time 1.01 seconds
Started Mar 10 01:38:17 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 216424 kb
Host smart-679dc79c-4569-4aee-8d0d-3f33bf96d7ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163763162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3163763162
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.4214023321
Short name T84
Test name
Test status
Simulation time 24189398 ps
CPU time 0.9 seconds
Started Mar 10 01:38:07 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 217064 kb
Host smart-48e85a15-322a-4580-88d2-8bfaeaf3ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214023321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.4214023321
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3560953647
Short name T514
Test name
Test status
Simulation time 45955181 ps
CPU time 1.73 seconds
Started Mar 10 01:38:01 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 216884 kb
Host smart-708027f8-dd21-4724-9203-1d061afba6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560953647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3560953647
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1617179438
Short name T784
Test name
Test status
Simulation time 24521737 ps
CPU time 1.07 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 222464 kb
Host smart-3177b86d-39cb-4018-88b6-f0adb36e00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617179438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1617179438
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1844697169
Short name T614
Test name
Test status
Simulation time 14978772 ps
CPU time 1.06 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:05 PM PDT 24
Peak memory 214380 kb
Host smart-19f686cd-abdb-4190-9d63-a6224a622de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844697169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1844697169
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1009429398
Short name T487
Test name
Test status
Simulation time 763675769 ps
CPU time 4.5 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:09 PM PDT 24
Peak memory 215672 kb
Host smart-297d3e81-8b27-4f16-ba19-9a95a6b36726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009429398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1009429398
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2492344204
Short name T713
Test name
Test status
Simulation time 147006413983 ps
CPU time 1243.59 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:58:48 PM PDT 24
Peak memory 223340 kb
Host smart-30e5b0b0-448f-430e-aac0-e3dbe01612e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492344204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2492344204
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3142141818
Short name T252
Test name
Test status
Simulation time 74215267 ps
CPU time 1.27 seconds
Started Mar 10 01:37:59 PM PDT 24
Finished Mar 10 01:38:02 PM PDT 24
Peak memory 214784 kb
Host smart-687d1447-fe65-47c7-b47e-05dca3c2c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142141818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3142141818
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3323104850
Short name T821
Test name
Test status
Simulation time 170454094 ps
CPU time 0.87 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 206040 kb
Host smart-18af4b13-06d5-4aac-b0a4-25eeeb6ee587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323104850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3323104850
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2596311440
Short name T303
Test name
Test status
Simulation time 42148544 ps
CPU time 0.85 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 214584 kb
Host smart-4a8680bd-333f-42f7-ab64-640d11b12dfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596311440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2596311440
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3126689526
Short name T223
Test name
Test status
Simulation time 26902227 ps
CPU time 1.18 seconds
Started Mar 10 01:37:58 PM PDT 24
Finished Mar 10 01:37:59 PM PDT 24
Peak memory 215400 kb
Host smart-73b5c3c1-411d-4475-8345-2bd57addf8c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126689526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3126689526
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.32532038
Short name T691
Test name
Test status
Simulation time 26807808 ps
CPU time 1.07 seconds
Started Mar 10 01:38:02 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 222160 kb
Host smart-1c4ecf6e-b5dc-42bd-88d5-3f7d1e7ee5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32532038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.32532038
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1914591514
Short name T590
Test name
Test status
Simulation time 40534249 ps
CPU time 1.53 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:02 PM PDT 24
Peak memory 216980 kb
Host smart-52a95bee-6b60-4658-ac51-5cc3d1188748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914591514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1914591514
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.4247235295
Short name T624
Test name
Test status
Simulation time 24536223 ps
CPU time 0.96 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 214772 kb
Host smart-d1931711-75a1-4e1b-800a-a1f8991b256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247235295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.4247235295
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1451326804
Short name T152
Test name
Test status
Simulation time 22665815 ps
CPU time 0.86 seconds
Started Mar 10 01:38:01 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 214400 kb
Host smart-5f6e3618-29b9-4bd4-94f1-a67eaccf5f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451326804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1451326804
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.942255764
Short name T827
Test name
Test status
Simulation time 77744739 ps
CPU time 1.28 seconds
Started Mar 10 01:37:58 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 214528 kb
Host smart-db9df593-0486-48c0-a3d3-cbcbbb2bd9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942255764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.942255764
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3835835350
Short name T400
Test name
Test status
Simulation time 79259423711 ps
CPU time 546.37 seconds
Started Mar 10 01:37:59 PM PDT 24
Finished Mar 10 01:47:07 PM PDT 24
Peak memory 217988 kb
Host smart-9df5477c-1d04-415b-926c-12e3139df349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835835350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3835835350
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3929865872
Short name T594
Test name
Test status
Simulation time 46140350 ps
CPU time 1.13 seconds
Started Mar 10 01:38:02 PM PDT 24
Finished Mar 10 01:38:05 PM PDT 24
Peak memory 214800 kb
Host smart-69721c98-71d7-4b57-bc38-d7c4eeffc9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929865872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3929865872
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.403961940
Short name T416
Test name
Test status
Simulation time 17199457 ps
CPU time 0.92 seconds
Started Mar 10 01:37:59 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 205732 kb
Host smart-62fa80c5-5ed3-4614-a322-bc04ec9db057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403961940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.403961940
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.148302097
Short name T155
Test name
Test status
Simulation time 22543060 ps
CPU time 0.9 seconds
Started Mar 10 01:38:02 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 214856 kb
Host smart-d49f714a-70ee-4344-908f-c4f80f9672cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148302097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.148302097
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.683095080
Short name T78
Test name
Test status
Simulation time 243870813 ps
CPU time 1.16 seconds
Started Mar 10 01:38:01 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 215516 kb
Host smart-8788cb3e-1cea-4f52-927b-aa2c67fe9546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683095080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.683095080
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.879377170
Short name T522
Test name
Test status
Simulation time 66089635 ps
CPU time 1.18 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 218240 kb
Host smart-e35f613c-87f4-475b-a156-ebc12f077af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879377170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.879377170
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.283950686
Short name T403
Test name
Test status
Simulation time 80592613 ps
CPU time 1.14 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 217836 kb
Host smart-febcd8bb-07ff-4c01-b357-bda9c5a462d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283950686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.283950686
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1216922979
Short name T597
Test name
Test status
Simulation time 23022574 ps
CPU time 1.18 seconds
Started Mar 10 01:37:57 PM PDT 24
Finished Mar 10 01:37:59 PM PDT 24
Peak memory 231740 kb
Host smart-e401bb98-0c2b-4496-9af2-e9a20717a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216922979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1216922979
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1971976292
Short name T311
Test name
Test status
Simulation time 48072229 ps
CPU time 0.95 seconds
Started Mar 10 01:38:02 PM PDT 24
Finished Mar 10 01:38:03 PM PDT 24
Peak memory 214344 kb
Host smart-2f66bb7d-c5ec-417c-8b65-1d942992388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971976292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1971976292
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3202861026
Short name T427
Test name
Test status
Simulation time 244156483 ps
CPU time 4.82 seconds
Started Mar 10 01:38:01 PM PDT 24
Finished Mar 10 01:38:07 PM PDT 24
Peak memory 218836 kb
Host smart-b4ec3972-7fb8-4379-ace2-53634e995684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202861026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3202861026
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.254121810
Short name T116
Test name
Test status
Simulation time 153750919 ps
CPU time 1.24 seconds
Started Mar 10 01:38:06 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 214788 kb
Host smart-4bfcadb7-dd4e-400f-b86e-4f70e4660cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254121810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.254121810
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3237762811
Short name T593
Test name
Test status
Simulation time 48143390 ps
CPU time 0.86 seconds
Started Mar 10 01:38:09 PM PDT 24
Finished Mar 10 01:38:10 PM PDT 24
Peak memory 205772 kb
Host smart-0709376e-b92e-490b-bd31-fa7102224b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237762811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3237762811
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3925047310
Short name T169
Test name
Test status
Simulation time 16594063 ps
CPU time 0.85 seconds
Started Mar 10 01:38:08 PM PDT 24
Finished Mar 10 01:38:09 PM PDT 24
Peak memory 215040 kb
Host smart-7b57d447-b9c2-4a28-a864-9bf691ad7d59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925047310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3925047310
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3636680639
Short name T530
Test name
Test status
Simulation time 25694230 ps
CPU time 1.02 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:05 PM PDT 24
Peak memory 222316 kb
Host smart-bb5cf5f3-4085-4ebe-b401-d07333d544cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636680639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3636680639
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2968008249
Short name T393
Test name
Test status
Simulation time 157326927 ps
CPU time 3.45 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 217096 kb
Host smart-3e153e5f-aefe-4edc-a174-90feb8bd2ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968008249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2968008249
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1407200761
Short name T378
Test name
Test status
Simulation time 27416889 ps
CPU time 0.95 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 214700 kb
Host smart-9a456439-042a-48fe-8680-6e3d675afa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407200761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1407200761
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3315032426
Short name T741
Test name
Test status
Simulation time 25757394 ps
CPU time 0.97 seconds
Started Mar 10 01:38:00 PM PDT 24
Finished Mar 10 01:38:01 PM PDT 24
Peak memory 214456 kb
Host smart-9ab817d2-aeca-4352-be6d-7847bd18ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315032426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3315032426
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.297356999
Short name T746
Test name
Test status
Simulation time 267137838 ps
CPU time 2.98 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:07 PM PDT 24
Peak memory 216852 kb
Host smart-e5869b5e-afbd-4493-85c5-fd8fd20ca821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297356999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.297356999
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3690196427
Short name T739
Test name
Test status
Simulation time 270277862598 ps
CPU time 3134.71 seconds
Started Mar 10 01:38:08 PM PDT 24
Finished Mar 10 02:30:24 PM PDT 24
Peak memory 229776 kb
Host smart-99363aca-c799-4ca3-a18d-c7bccaab44a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690196427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3690196427
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.709181200
Short name T183
Test name
Test status
Simulation time 70924557 ps
CPU time 1.28 seconds
Started Mar 10 01:38:07 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 214820 kb
Host smart-69bdd769-0762-4c47-a730-398810c144d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709181200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.709181200
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3599052253
Short name T430
Test name
Test status
Simulation time 42270081 ps
CPU time 0.87 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:05 PM PDT 24
Peak memory 205948 kb
Host smart-5f4ab325-fc7c-4558-bfa3-3ae4805af27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599052253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3599052253
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3848061314
Short name T181
Test name
Test status
Simulation time 22776417 ps
CPU time 0.85 seconds
Started Mar 10 01:38:02 PM PDT 24
Finished Mar 10 01:38:04 PM PDT 24
Peak memory 214900 kb
Host smart-8ccece58-a789-41de-be64-780bec52a4cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848061314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3848061314
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.32672118
Short name T832
Test name
Test status
Simulation time 51164508 ps
CPU time 1.14 seconds
Started Mar 10 01:38:06 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 215560 kb
Host smart-e285f7d7-2f80-4e9f-b2a3-cd4f5592b84f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_dis
able_auto_req_mode.32672118
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2751481830
Short name T57
Test name
Test status
Simulation time 19499510 ps
CPU time 1.06 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 217096 kb
Host smart-56e78349-07c9-46dd-aece-63962ff012b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751481830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2751481830
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3161843318
Short name T363
Test name
Test status
Simulation time 39023356 ps
CPU time 1.6 seconds
Started Mar 10 01:38:17 PM PDT 24
Finished Mar 10 01:38:19 PM PDT 24
Peak memory 216900 kb
Host smart-beb04f5d-729e-4c07-a6aa-992b5aa88a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161843318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3161843318
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2353622256
Short name T118
Test name
Test status
Simulation time 23566785 ps
CPU time 0.94 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 214544 kb
Host smart-7bef591c-41ef-4592-9c61-a31a0bcf464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353622256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2353622256
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4292749110
Short name T396
Test name
Test status
Simulation time 219736164 ps
CPU time 0.89 seconds
Started Mar 10 01:38:17 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 214264 kb
Host smart-9a056726-ff88-4351-9509-0a6c446e6411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292749110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4292749110
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2509392753
Short name T776
Test name
Test status
Simulation time 489602388 ps
CPU time 3.29 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:09 PM PDT 24
Peak memory 218120 kb
Host smart-b6cb8f1b-fd1f-4e8b-b1c4-6e916ae30c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509392753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2509392753
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3655495576
Short name T615
Test name
Test status
Simulation time 35496803885 ps
CPU time 317.44 seconds
Started Mar 10 01:38:06 PM PDT 24
Finished Mar 10 01:43:24 PM PDT 24
Peak memory 218440 kb
Host smart-930a9198-5793-4163-b827-22e3bf752844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655495576 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3655495576
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3892570149
Short name T839
Test name
Test status
Simulation time 25514230 ps
CPU time 1.25 seconds
Started Mar 10 01:36:25 PM PDT 24
Finished Mar 10 01:36:26 PM PDT 24
Peak memory 214772 kb
Host smart-4f065be3-4d06-42c0-bd2a-66e6ce58d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892570149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3892570149
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4024259834
Short name T525
Test name
Test status
Simulation time 62741427 ps
CPU time 0.89 seconds
Started Mar 10 01:36:21 PM PDT 24
Finished Mar 10 01:36:22 PM PDT 24
Peak memory 205788 kb
Host smart-cf0119c2-cbda-4a07-814d-fa2df42552a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024259834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4024259834
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3375397528
Short name T623
Test name
Test status
Simulation time 23743256 ps
CPU time 0.91 seconds
Started Mar 10 01:36:21 PM PDT 24
Finished Mar 10 01:36:21 PM PDT 24
Peak memory 214832 kb
Host smart-86914c8a-68b1-4813-84d6-d6af26c2fc66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375397528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3375397528
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3440674733
Short name T164
Test name
Test status
Simulation time 319346189 ps
CPU time 1.05 seconds
Started Mar 10 01:36:22 PM PDT 24
Finished Mar 10 01:36:23 PM PDT 24
Peak memory 215544 kb
Host smart-635a40fb-d5c0-4c87-9cd2-b939c7a49e78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440674733 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3440674733
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3139774425
Short name T158
Test name
Test status
Simulation time 25349291 ps
CPU time 1.21 seconds
Started Mar 10 01:36:19 PM PDT 24
Finished Mar 10 01:36:21 PM PDT 24
Peak memory 219252 kb
Host smart-578aef4f-abd5-44b7-834b-d8979f221e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139774425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3139774425
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3103528689
Short name T280
Test name
Test status
Simulation time 165318370 ps
CPU time 3.2 seconds
Started Mar 10 01:36:18 PM PDT 24
Finished Mar 10 01:36:21 PM PDT 24
Peak memory 215848 kb
Host smart-7ba69982-eeb4-461b-90dc-06ad79eb648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103528689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3103528689
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.437651451
Short name T752
Test name
Test status
Simulation time 28498912 ps
CPU time 0.9 seconds
Started Mar 10 01:36:15 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 214772 kb
Host smart-08bccc88-0025-4629-bdfa-c398b59de280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437651451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.437651451
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2952648186
Short name T249
Test name
Test status
Simulation time 19841211 ps
CPU time 1.05 seconds
Started Mar 10 01:36:18 PM PDT 24
Finished Mar 10 01:36:19 PM PDT 24
Peak memory 206200 kb
Host smart-a5c8f72b-c7ff-4f82-af1d-5ead458899fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952648186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2952648186
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1052154723
Short name T458
Test name
Test status
Simulation time 69964803 ps
CPU time 0.9 seconds
Started Mar 10 01:36:22 PM PDT 24
Finished Mar 10 01:36:23 PM PDT 24
Peak memory 214372 kb
Host smart-0a354340-2acd-4042-ae19-6426d7342765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052154723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1052154723
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1486964864
Short name T658
Test name
Test status
Simulation time 228095725 ps
CPU time 2.62 seconds
Started Mar 10 01:36:19 PM PDT 24
Finished Mar 10 01:36:22 PM PDT 24
Peak memory 214380 kb
Host smart-b370a464-b603-4302-b6d1-42bad5ef532e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486964864 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1486964864
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4174887810
Short name T678
Test name
Test status
Simulation time 60806909874 ps
CPU time 1021.12 seconds
Started Mar 10 01:36:20 PM PDT 24
Finished Mar 10 01:53:22 PM PDT 24
Peak memory 217920 kb
Host smart-33573b33-e578-4539-8647-17ff0b0b5eb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174887810 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4174887810
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3496175555
Short name T103
Test name
Test status
Simulation time 28958244 ps
CPU time 0.86 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 217060 kb
Host smart-b5b67e23-ffbe-4fba-aecd-805259bd5da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496175555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3496175555
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1042322006
Short name T513
Test name
Test status
Simulation time 251544909 ps
CPU time 1.2 seconds
Started Mar 10 01:38:04 PM PDT 24
Finished Mar 10 01:38:05 PM PDT 24
Peak memory 215824 kb
Host smart-21ff9602-ec3f-4fa8-be7f-1b9f4c0209e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042322006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1042322006
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.58774816
Short name T716
Test name
Test status
Simulation time 28515333 ps
CPU time 1.38 seconds
Started Mar 10 01:38:05 PM PDT 24
Finished Mar 10 01:38:06 PM PDT 24
Peak memory 228744 kb
Host smart-83e3657d-52e8-4b33-8704-daf39bbe4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58774816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.58774816
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2015783895
Short name T14
Test name
Test status
Simulation time 157878275 ps
CPU time 1.71 seconds
Started Mar 10 01:38:06 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 216868 kb
Host smart-d5dc61c8-a537-4184-b6dd-43a432747952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015783895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2015783895
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3266763073
Short name T5
Test name
Test status
Simulation time 19066852 ps
CPU time 1.08 seconds
Started Mar 10 01:38:08 PM PDT 24
Finished Mar 10 01:38:09 PM PDT 24
Peak memory 217280 kb
Host smart-228eac5a-5ef8-4e29-8feb-c8ee606d0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266763073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3266763073
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1272844253
Short name T510
Test name
Test status
Simulation time 46569449 ps
CPU time 1.21 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 216608 kb
Host smart-0d8c2ca1-a789-4dbd-bb78-bccf6ecf7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272844253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1272844253
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.442478035
Short name T707
Test name
Test status
Simulation time 28578152 ps
CPU time 0.84 seconds
Started Mar 10 01:38:10 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 216880 kb
Host smart-752c57a2-569d-41de-92a2-5d86e64151b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442478035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.442478035
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2255816870
Short name T667
Test name
Test status
Simulation time 55421281 ps
CPU time 1.51 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 216680 kb
Host smart-0e6ae848-8820-43db-954a-75d6a7fdf7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255816870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2255816870
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.330458972
Short name T608
Test name
Test status
Simulation time 21501901 ps
CPU time 1.11 seconds
Started Mar 10 01:38:10 PM PDT 24
Finished Mar 10 01:38:12 PM PDT 24
Peak memory 222216 kb
Host smart-7b8a938d-5c61-47f2-8078-677b9aa41f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330458972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.330458972
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1935373409
Short name T462
Test name
Test status
Simulation time 45913476 ps
CPU time 1.29 seconds
Started Mar 10 01:38:09 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 215612 kb
Host smart-64a72761-e442-4f1f-a740-9623822f818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935373409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1935373409
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2679995728
Short name T418
Test name
Test status
Simulation time 19197006 ps
CPU time 1.11 seconds
Started Mar 10 01:38:11 PM PDT 24
Finished Mar 10 01:38:12 PM PDT 24
Peak memory 217380 kb
Host smart-1cea2ac7-13dc-4931-b91a-4889436ce12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679995728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2679995728
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1104914456
Short name T649
Test name
Test status
Simulation time 27627418 ps
CPU time 1.34 seconds
Started Mar 10 01:38:10 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 216020 kb
Host smart-4a85d702-c9da-41fb-ac97-38b48e7af63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104914456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1104914456
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3685092104
Short name T6
Test name
Test status
Simulation time 24776139 ps
CPU time 0.96 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 218464 kb
Host smart-1e0b1d9c-e44a-4ee9-aba0-5c81d7e74968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685092104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3685092104
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2932915781
Short name T406
Test name
Test status
Simulation time 162865938 ps
CPU time 2.12 seconds
Started Mar 10 01:38:12 PM PDT 24
Finished Mar 10 01:38:14 PM PDT 24
Peak memory 215972 kb
Host smart-435a8026-68c1-44f0-b36d-a8e7725147a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932915781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2932915781
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.850460103
Short name T466
Test name
Test status
Simulation time 23818633 ps
CPU time 1.14 seconds
Started Mar 10 01:38:09 PM PDT 24
Finished Mar 10 01:38:10 PM PDT 24
Peak memory 217232 kb
Host smart-8c4342cb-88f8-4d5d-87ca-d6e9f948320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850460103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.850460103
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1628909928
Short name T358
Test name
Test status
Simulation time 164854668 ps
CPU time 2.38 seconds
Started Mar 10 01:38:11 PM PDT 24
Finished Mar 10 01:38:14 PM PDT 24
Peak memory 218196 kb
Host smart-bc8e21e1-0582-4371-8930-7819d6ccdaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628909928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1628909928
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2242024011
Short name T557
Test name
Test status
Simulation time 79047455 ps
CPU time 0.99 seconds
Started Mar 10 01:38:07 PM PDT 24
Finished Mar 10 01:38:08 PM PDT 24
Peak memory 216008 kb
Host smart-43a57214-86bd-4150-993f-fd5be233cfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242024011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2242024011
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3967245770
Short name T715
Test name
Test status
Simulation time 96563128 ps
CPU time 1.5 seconds
Started Mar 10 01:38:09 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 217312 kb
Host smart-d14bd702-4178-425f-a042-561e97bfc531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967245770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3967245770
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.920572470
Short name T433
Test name
Test status
Simulation time 40678933 ps
CPU time 0.81 seconds
Started Mar 10 01:38:11 PM PDT 24
Finished Mar 10 01:38:12 PM PDT 24
Peak memory 217044 kb
Host smart-3983eea5-df70-4eaa-8add-d758d5a096b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920572470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.920572470
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1173697206
Short name T459
Test name
Test status
Simulation time 61836043 ps
CPU time 1.6 seconds
Started Mar 10 01:38:10 PM PDT 24
Finished Mar 10 01:38:12 PM PDT 24
Peak memory 216944 kb
Host smart-cf7caa5f-493c-45bc-a4c7-8e1e2f031151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173697206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1173697206
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1909400340
Short name T819
Test name
Test status
Simulation time 26284311 ps
CPU time 1.27 seconds
Started Mar 10 01:36:18 PM PDT 24
Finished Mar 10 01:36:20 PM PDT 24
Peak memory 214800 kb
Host smart-5675d5be-9306-465d-b97d-4cb310ba872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909400340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1909400340
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2334353367
Short name T298
Test name
Test status
Simulation time 11923720 ps
CPU time 0.86 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:24 PM PDT 24
Peak memory 205176 kb
Host smart-30f038b7-bb26-421c-b765-7ee37f44d0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334353367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2334353367
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3869635587
Short name T411
Test name
Test status
Simulation time 33656633 ps
CPU time 0.8 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:23 PM PDT 24
Peak memory 214748 kb
Host smart-b8bf3e9f-dfea-495e-b824-e80794c83b3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869635587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3869635587
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.2373390434
Short name T80
Test name
Test status
Simulation time 45257863 ps
CPU time 1.03 seconds
Started Mar 10 01:36:17 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 215828 kb
Host smart-ddd2531d-a745-457e-8002-cb0a442f4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373390434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2373390434
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.473088583
Short name T440
Test name
Test status
Simulation time 54376171 ps
CPU time 1.56 seconds
Started Mar 10 01:36:18 PM PDT 24
Finished Mar 10 01:36:19 PM PDT 24
Peak memory 216740 kb
Host smart-f8bba4de-233a-430f-b78b-bdf9e2bd5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473088583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.473088583
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3447503361
Short name T58
Test name
Test status
Simulation time 24303235 ps
CPU time 0.94 seconds
Started Mar 10 01:36:20 PM PDT 24
Finished Mar 10 01:36:21 PM PDT 24
Peak memory 214728 kb
Host smart-4c1f8473-941f-4948-bf02-167ef4206ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447503361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3447503361
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.900303335
Short name T437
Test name
Test status
Simulation time 49936325 ps
CPU time 0.95 seconds
Started Mar 10 01:36:17 PM PDT 24
Finished Mar 10 01:36:18 PM PDT 24
Peak memory 214408 kb
Host smart-ce992c8e-5450-49e0-8e81-1f35a02b38ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900303335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.900303335
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1402024612
Short name T599
Test name
Test status
Simulation time 143628819 ps
CPU time 3.21 seconds
Started Mar 10 01:36:20 PM PDT 24
Finished Mar 10 01:36:23 PM PDT 24
Peak memory 216824 kb
Host smart-c9764ea6-79ae-4b25-9504-86f28748ac0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402024612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1402024612
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3137177688
Short name T813
Test name
Test status
Simulation time 58225366040 ps
CPU time 1349.07 seconds
Started Mar 10 01:36:19 PM PDT 24
Finished Mar 10 01:58:49 PM PDT 24
Peak memory 220244 kb
Host smart-ea4de816-ef65-4971-be7f-a0b5017a2e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137177688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3137177688
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1961500602
Short name T68
Test name
Test status
Simulation time 94986015 ps
CPU time 1 seconds
Started Mar 10 01:38:11 PM PDT 24
Finished Mar 10 01:38:13 PM PDT 24
Peak memory 215968 kb
Host smart-3c64a48b-01ad-4300-be70-e27819dd6fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961500602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1961500602
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3620652698
Short name T642
Test name
Test status
Simulation time 27552565 ps
CPU time 1.13 seconds
Started Mar 10 01:38:08 PM PDT 24
Finished Mar 10 01:38:10 PM PDT 24
Peak memory 215488 kb
Host smart-f1d79e78-506d-4284-8355-bb1e8b02b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620652698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3620652698
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2986309850
Short name T626
Test name
Test status
Simulation time 19232197 ps
CPU time 1.21 seconds
Started Mar 10 01:38:12 PM PDT 24
Finished Mar 10 01:38:13 PM PDT 24
Peak memory 230480 kb
Host smart-905d3787-eecf-4ff7-a220-80bd9c8d7fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986309850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2986309850
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1753036666
Short name T695
Test name
Test status
Simulation time 84062152 ps
CPU time 1.3 seconds
Started Mar 10 01:38:09 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 217148 kb
Host smart-9e80df18-2aff-4c9a-91cd-1137ea1349e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753036666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1753036666
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1053038628
Short name T663
Test name
Test status
Simulation time 27019260 ps
CPU time 0.86 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 216696 kb
Host smart-1ca5052d-b860-49c6-89c5-ba1a1e0c8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053038628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1053038628
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.4088406666
Short name T371
Test name
Test status
Simulation time 70112312 ps
CPU time 1.2 seconds
Started Mar 10 01:38:15 PM PDT 24
Finished Mar 10 01:38:16 PM PDT 24
Peak memory 215488 kb
Host smart-28ce31be-d088-4696-8289-093125e619d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088406666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4088406666
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.243000690
Short name T676
Test name
Test status
Simulation time 26804928 ps
CPU time 1.32 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 230560 kb
Host smart-a83f86a0-58bb-48b8-ab8c-b903656894c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243000690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.243000690
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2566993942
Short name T645
Test name
Test status
Simulation time 35680167 ps
CPU time 1.42 seconds
Started Mar 10 01:38:15 PM PDT 24
Finished Mar 10 01:38:16 PM PDT 24
Peak memory 217004 kb
Host smart-00c6ec19-a261-430f-b7ce-338ccd2c6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566993942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2566993942
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.41568718
Short name T99
Test name
Test status
Simulation time 28225022 ps
CPU time 0.98 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 222280 kb
Host smart-c4b3c2e1-c41e-44c8-a316-212ee091dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41568718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.41568718
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2070536722
Short name T717
Test name
Test status
Simulation time 45665576 ps
CPU time 1.1 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 215544 kb
Host smart-af3a792c-43c7-4716-955f-d55ec012fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070536722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2070536722
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.614082051
Short name T372
Test name
Test status
Simulation time 19856426 ps
CPU time 1.12 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 222240 kb
Host smart-eabe200f-4e5e-4844-8198-28a3f15afd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614082051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.614082051
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.305835691
Short name T840
Test name
Test status
Simulation time 54979201 ps
CPU time 1.48 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 216976 kb
Host smart-1c01f799-baa2-4730-913b-95ff837dbe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305835691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.305835691
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1455933841
Short name T445
Test name
Test status
Simulation time 65250715 ps
CPU time 0.77 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:21 PM PDT 24
Peak memory 217096 kb
Host smart-9a269b49-6d50-4696-a27b-4b080e04849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455933841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1455933841
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3484626559
Short name T581
Test name
Test status
Simulation time 71765825 ps
CPU time 1.34 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 217236 kb
Host smart-e5ac5e2e-272e-4256-90fd-e3b89b4faa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484626559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3484626559
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.245806450
Short name T409
Test name
Test status
Simulation time 25454916 ps
CPU time 1.18 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 218584 kb
Host smart-75be22a5-fc29-4cc8-9ecf-bbbafdf253e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245806450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.245806450
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2065708322
Short name T429
Test name
Test status
Simulation time 70766778 ps
CPU time 1.21 seconds
Started Mar 10 01:38:15 PM PDT 24
Finished Mar 10 01:38:16 PM PDT 24
Peak memory 215664 kb
Host smart-c3ef6361-5399-4f5d-96cf-427fafd28e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065708322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2065708322
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1286121061
Short name T321
Test name
Test status
Simulation time 26921963 ps
CPU time 0.86 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 217100 kb
Host smart-77bebe27-8e68-4a9d-817e-3f9e23fa67d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286121061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1286121061
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1857992918
Short name T719
Test name
Test status
Simulation time 69575672 ps
CPU time 1.3 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:14 PM PDT 24
Peak memory 215816 kb
Host smart-4f88545e-2a2d-4e51-82eb-906271b38547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857992918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1857992918
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2144582687
Short name T50
Test name
Test status
Simulation time 33954920 ps
CPU time 1.03 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 228908 kb
Host smart-20e0e423-e577-495f-a275-4a259232a4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144582687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2144582687
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3043726193
Short name T387
Test name
Test status
Simulation time 166521694 ps
CPU time 3.5 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 216904 kb
Host smart-39d0114f-4441-4113-9048-cc596a7ddec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043726193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3043726193
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1789700828
Short name T248
Test name
Test status
Simulation time 374009736 ps
CPU time 1.59 seconds
Started Mar 10 01:36:24 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 214788 kb
Host smart-04fb503b-a700-4be8-9fbd-9a3d9c39d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789700828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1789700828
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2617586223
Short name T675
Test name
Test status
Simulation time 28736141 ps
CPU time 0.93 seconds
Started Mar 10 01:36:24 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 206076 kb
Host smart-4a152f03-30cf-40b6-89ae-9db4fbcaf08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617586223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2617586223
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_err.2828496706
Short name T481
Test name
Test status
Simulation time 29676704 ps
CPU time 0.94 seconds
Started Mar 10 01:36:25 PM PDT 24
Finished Mar 10 01:36:26 PM PDT 24
Peak memory 222184 kb
Host smart-ea3ed4de-88e6-41f3-a115-4502b3b596f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828496706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2828496706
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1158818552
Short name T290
Test name
Test status
Simulation time 48151877 ps
CPU time 1.43 seconds
Started Mar 10 01:36:24 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 216676 kb
Host smart-226ea24e-a24f-45c3-a927-5954875616ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158818552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1158818552
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.809613893
Short name T529
Test name
Test status
Simulation time 25551493 ps
CPU time 1.12 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 222328 kb
Host smart-04526675-14cd-4795-8ab4-5e30fadbf6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809613893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.809613893
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2949184016
Short name T254
Test name
Test status
Simulation time 17292137 ps
CPU time 0.99 seconds
Started Mar 10 01:36:21 PM PDT 24
Finished Mar 10 01:36:22 PM PDT 24
Peak memory 206204 kb
Host smart-ce320c40-eada-4805-9a5f-4b5cf7c60e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949184016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2949184016
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2361120139
Short name T762
Test name
Test status
Simulation time 41961649 ps
CPU time 0.91 seconds
Started Mar 10 01:36:24 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 214448 kb
Host smart-2bfdd91f-cab4-4654-86e2-bae576d02562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361120139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2361120139
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2423608936
Short name T732
Test name
Test status
Simulation time 277783975 ps
CPU time 4.65 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:28 PM PDT 24
Peak memory 215412 kb
Host smart-8bd8f156-8604-4239-85e4-f83113d37563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423608936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2423608936
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1214047148
Short name T509
Test name
Test status
Simulation time 38804762816 ps
CPU time 446.16 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:43:50 PM PDT 24
Peak memory 222768 kb
Host smart-8de4495b-e4bb-414c-a789-ae9a0920c9a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214047148 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1214047148
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1063057594
Short name T726
Test name
Test status
Simulation time 24611845 ps
CPU time 1.06 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 222392 kb
Host smart-c21af0fc-27eb-41e3-9b94-4df9c6ddc948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063057594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1063057594
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1303813924
Short name T435
Test name
Test status
Simulation time 49569847 ps
CPU time 1.31 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:14 PM PDT 24
Peak memory 215612 kb
Host smart-93028e9b-f52d-499b-bdf1-d5d19adb1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303813924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1303813924
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3358497814
Short name T93
Test name
Test status
Simulation time 25211989 ps
CPU time 0.95 seconds
Started Mar 10 01:38:14 PM PDT 24
Finished Mar 10 01:38:15 PM PDT 24
Peak memory 217180 kb
Host smart-c8418b3f-50e3-4115-9797-2db2a85237e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358497814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3358497814
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.133355243
Short name T275
Test name
Test status
Simulation time 191829968 ps
CPU time 2.82 seconds
Started Mar 10 01:38:15 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 217620 kb
Host smart-61cd7aee-bee3-46c1-bcbd-678a50013e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133355243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.133355243
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.4183545915
Short name T111
Test name
Test status
Simulation time 31797148 ps
CPU time 0.96 seconds
Started Mar 10 01:38:13 PM PDT 24
Finished Mar 10 01:38:14 PM PDT 24
Peak memory 230404 kb
Host smart-8bba0939-8720-450b-a6be-27c5fcfe1876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183545915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4183545915
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4293529034
Short name T408
Test name
Test status
Simulation time 74714980 ps
CPU time 1.29 seconds
Started Mar 10 01:38:16 PM PDT 24
Finished Mar 10 01:38:17 PM PDT 24
Peak memory 217052 kb
Host smart-6cb0aa28-6179-4894-8047-49a260c6c236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293529034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4293529034
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.4174261794
Short name T547
Test name
Test status
Simulation time 20402629 ps
CPU time 1.13 seconds
Started Mar 10 01:38:19 PM PDT 24
Finished Mar 10 01:38:21 PM PDT 24
Peak memory 218592 kb
Host smart-96ddea3b-1b08-425c-bb6b-53fa3b3bf6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174261794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4174261794
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3519540049
Short name T495
Test name
Test status
Simulation time 323398336 ps
CPU time 1.21 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 215812 kb
Host smart-af395d8c-aadd-4f96-928f-508468086b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519540049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3519540049
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4103293708
Short name T734
Test name
Test status
Simulation time 98280734 ps
CPU time 0.9 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:19 PM PDT 24
Peak memory 217160 kb
Host smart-8a111fa8-bba4-4b70-beb3-950624ae5d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103293708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4103293708
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3306096254
Short name T457
Test name
Test status
Simulation time 29861379 ps
CPU time 1.26 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 215488 kb
Host smart-541e88cf-3276-49be-9800-4820cbc665c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306096254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3306096254
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3389891770
Short name T472
Test name
Test status
Simulation time 32072629 ps
CPU time 0.96 seconds
Started Mar 10 01:38:17 PM PDT 24
Finished Mar 10 01:38:18 PM PDT 24
Peak memory 222176 kb
Host smart-9acce7ad-b584-4216-9f3b-610fd2a77dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389891770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3389891770
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2518068491
Short name T368
Test name
Test status
Simulation time 159096381 ps
CPU time 1.56 seconds
Started Mar 10 01:38:19 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 215876 kb
Host smart-f1e303b5-6172-492d-8d49-5cfecd202ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518068491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2518068491
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.354607673
Short name T576
Test name
Test status
Simulation time 34580161 ps
CPU time 1.05 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 217288 kb
Host smart-6e16e8de-0bd5-4e84-94be-741567e54692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354607673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.354607673
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3225694614
Short name T380
Test name
Test status
Simulation time 101302605 ps
CPU time 1.22 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 216820 kb
Host smart-8a75d1e1-492c-4d4a-a999-4c5f3c46205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225694614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3225694614
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3532253799
Short name T612
Test name
Test status
Simulation time 18552011 ps
CPU time 1.08 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 217064 kb
Host smart-9d5e269e-e4a5-4cdb-91d6-0ab888991faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532253799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3532253799
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1349447780
Short name T265
Test name
Test status
Simulation time 64744922 ps
CPU time 1.19 seconds
Started Mar 10 01:38:17 PM PDT 24
Finished Mar 10 01:38:19 PM PDT 24
Peak memory 215716 kb
Host smart-4c36afc1-0e65-490b-b723-0ef3085eb1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349447780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1349447780
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2372281761
Short name T587
Test name
Test status
Simulation time 26921713 ps
CPU time 0.83 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:21 PM PDT 24
Peak memory 216964 kb
Host smart-3c854d1e-bed5-452e-a4e1-ecc736be1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372281761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2372281761
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1751190091
Short name T276
Test name
Test status
Simulation time 56906602 ps
CPU time 1.29 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 218400 kb
Host smart-48975f98-61ea-411a-9035-4e812e243659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751190091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1751190091
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3568124361
Short name T835
Test name
Test status
Simulation time 31644298 ps
CPU time 0.98 seconds
Started Mar 10 01:38:19 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 222288 kb
Host smart-bcfef8ef-d63f-4318-9a34-5ab4f23f036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568124361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3568124361
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4095930386
Short name T369
Test name
Test status
Simulation time 43564894 ps
CPU time 1.81 seconds
Started Mar 10 01:38:18 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 216776 kb
Host smart-4fbce302-ba7e-4495-92d0-2a84599c2d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095930386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4095930386
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1451347925
Short name T20
Test name
Test status
Simulation time 30584693 ps
CPU time 1.39 seconds
Started Mar 10 01:36:30 PM PDT 24
Finished Mar 10 01:36:32 PM PDT 24
Peak memory 214784 kb
Host smart-005d440e-fc4c-47ae-a3d3-a3ef1a95fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451347925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1451347925
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1318439998
Short name T432
Test name
Test status
Simulation time 17075711 ps
CPU time 0.98 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 205660 kb
Host smart-4e07db2e-7dae-4acd-9edb-c6fa30bd20ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318439998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1318439998
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2995136119
Short name T89
Test name
Test status
Simulation time 23046190 ps
CPU time 0.93 seconds
Started Mar 10 01:36:28 PM PDT 24
Finished Mar 10 01:36:29 PM PDT 24
Peak memory 214648 kb
Host smart-55ec2291-453b-4fb2-a38c-9e7ac1cd4265
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995136119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2995136119
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.124651877
Short name T352
Test name
Test status
Simulation time 18214608 ps
CPU time 1.03 seconds
Started Mar 10 01:36:28 PM PDT 24
Finished Mar 10 01:36:30 PM PDT 24
Peak memory 216996 kb
Host smart-c2108336-6287-4483-83f0-169d879223a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124651877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.124651877
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.830935056
Short name T568
Test name
Test status
Simulation time 58998074 ps
CPU time 1.32 seconds
Started Mar 10 01:36:28 PM PDT 24
Finished Mar 10 01:36:29 PM PDT 24
Peak memory 215692 kb
Host smart-1e4b234d-5d90-464d-b8ef-4dff9d5777fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830935056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.830935056
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3831929659
Short name T501
Test name
Test status
Simulation time 24424775 ps
CPU time 1.14 seconds
Started Mar 10 01:36:29 PM PDT 24
Finished Mar 10 01:36:30 PM PDT 24
Peak memory 214532 kb
Host smart-23e3c9ec-c3b7-4bfe-80bd-d93e0174662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831929659 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3831929659
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3013926203
Short name T121
Test name
Test status
Simulation time 18422631 ps
CPU time 0.97 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 206132 kb
Host smart-a94ba8f3-4778-46db-a313-f82360aace78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013926203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3013926203
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.703216374
Short name T596
Test name
Test status
Simulation time 96398447 ps
CPU time 0.94 seconds
Started Mar 10 01:36:23 PM PDT 24
Finished Mar 10 01:36:25 PM PDT 24
Peak memory 214380 kb
Host smart-52692917-85dc-4ded-9485-6f34cb8039dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703216374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.703216374
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1004317488
Short name T814
Test name
Test status
Simulation time 114436654 ps
CPU time 2.57 seconds
Started Mar 10 01:36:28 PM PDT 24
Finished Mar 10 01:36:31 PM PDT 24
Peak memory 215368 kb
Host smart-c91277fe-017b-47f4-bbc1-b264e0b03b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004317488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1004317488
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2205814711
Short name T769
Test name
Test status
Simulation time 38446330268 ps
CPU time 856.92 seconds
Started Mar 10 01:36:29 PM PDT 24
Finished Mar 10 01:50:46 PM PDT 24
Peak memory 217068 kb
Host smart-c0c8af7e-72c3-4c4c-9c72-48b7617ba111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205814711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2205814711
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1768831308
Short name T73
Test name
Test status
Simulation time 61302183 ps
CPU time 0.9 seconds
Started Mar 10 01:38:19 PM PDT 24
Finished Mar 10 01:38:20 PM PDT 24
Peak memory 217096 kb
Host smart-ef962019-213c-40fe-b765-9612fa343af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768831308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1768831308
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4160898047
Short name T664
Test name
Test status
Simulation time 139616805 ps
CPU time 1.13 seconds
Started Mar 10 01:38:21 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 217184 kb
Host smart-8687d9dd-1452-46a4-bff5-38567d09b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160898047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4160898047
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1011772235
Short name T683
Test name
Test status
Simulation time 32006935 ps
CPU time 0.85 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:21 PM PDT 24
Peak memory 216712 kb
Host smart-204c0dbc-d44f-487e-a191-a73bb51836da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011772235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1011772235
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2678326484
Short name T699
Test name
Test status
Simulation time 98941970 ps
CPU time 1.3 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 217116 kb
Host smart-bf3ae1c6-6926-4439-ab36-01add1740c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678326484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2678326484
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1743051604
Short name T69
Test name
Test status
Simulation time 25361790 ps
CPU time 1 seconds
Started Mar 10 01:38:21 PM PDT 24
Finished Mar 10 01:38:23 PM PDT 24
Peak memory 218344 kb
Host smart-ea2ebefb-2f47-4da6-8dd9-0f2dd56fddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743051604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1743051604
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1770978088
Short name T665
Test name
Test status
Simulation time 96954339 ps
CPU time 1.41 seconds
Started Mar 10 01:38:21 PM PDT 24
Finished Mar 10 01:38:23 PM PDT 24
Peak memory 215824 kb
Host smart-70dc0dfd-2e05-4e4e-8866-a2530a73a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770978088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1770978088
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1884750434
Short name T90
Test name
Test status
Simulation time 81096394 ps
CPU time 0.85 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 216988 kb
Host smart-86aabc7e-d1f3-4885-b883-48298f1b0675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884750434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1884750434
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3051104159
Short name T722
Test name
Test status
Simulation time 35380903 ps
CPU time 1.45 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 216972 kb
Host smart-b0fe0000-db7e-4bb8-871e-550adb694206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051104159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3051104159
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3132469595
Short name T646
Test name
Test status
Simulation time 21956779 ps
CPU time 1.19 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 218396 kb
Host smart-b32e0b99-3ecd-4d52-8416-1823705e4c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132469595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3132469595
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.686356239
Short name T629
Test name
Test status
Simulation time 26711401 ps
CPU time 1.11 seconds
Started Mar 10 01:38:20 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 214396 kb
Host smart-dd16dd21-1bf8-4b1b-8d04-c2241aa28480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686356239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.686356239
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2060973359
Short name T617
Test name
Test status
Simulation time 47572957 ps
CPU time 0.85 seconds
Started Mar 10 01:38:26 PM PDT 24
Finished Mar 10 01:38:27 PM PDT 24
Peak memory 216824 kb
Host smart-d2d970f0-d457-49e6-9018-023698ad0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060973359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2060973359
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2680269588
Short name T806
Test name
Test status
Simulation time 60013850 ps
CPU time 1.41 seconds
Started Mar 10 01:38:21 PM PDT 24
Finished Mar 10 01:38:22 PM PDT 24
Peak memory 216828 kb
Host smart-06cad942-f1d5-40dd-a22b-a3c2bbc3a949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680269588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2680269588
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1435310637
Short name T167
Test name
Test status
Simulation time 55519217 ps
CPU time 1.08 seconds
Started Mar 10 01:38:23 PM PDT 24
Finished Mar 10 01:38:24 PM PDT 24
Peak memory 228936 kb
Host smart-f06fed49-c84f-41ae-a36e-35989c87a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435310637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1435310637
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1423606791
Short name T37
Test name
Test status
Simulation time 49966216 ps
CPU time 1.75 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 216676 kb
Host smart-d1e2b681-fbcb-400a-9ea0-f8232e9e3f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423606791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1423606791
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3788697126
Short name T85
Test name
Test status
Simulation time 51342330 ps
CPU time 1.25 seconds
Started Mar 10 01:38:23 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 231492 kb
Host smart-398f7c39-eef1-45a1-a683-abdc77a9848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788697126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3788697126
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.373241584
Short name T340
Test name
Test status
Simulation time 35360178 ps
CPU time 1.31 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 215400 kb
Host smart-baf94542-caaf-44e1-b6e2-e98eed28b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373241584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.373241584
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1303557805
Short name T661
Test name
Test status
Simulation time 36041132 ps
CPU time 1.08 seconds
Started Mar 10 01:38:23 PM PDT 24
Finished Mar 10 01:38:24 PM PDT 24
Peak memory 215828 kb
Host smart-0b7c8fe3-8c39-4e1b-9630-b9d9a3eb54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303557805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1303557805
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.81258814
Short name T772
Test name
Test status
Simulation time 33941798 ps
CPU time 1.25 seconds
Started Mar 10 01:38:22 PM PDT 24
Finished Mar 10 01:38:24 PM PDT 24
Peak memory 216936 kb
Host smart-88b6d56c-faca-413e-a11c-8bc44014c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81258814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.81258814
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3040928412
Short name T76
Test name
Test status
Simulation time 61318231 ps
CPU time 0.98 seconds
Started Mar 10 01:38:27 PM PDT 24
Finished Mar 10 01:38:29 PM PDT 24
Peak memory 219124 kb
Host smart-36594fa1-568e-431b-a3a4-0c5136ccc238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040928412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3040928412
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2901426876
Short name T809
Test name
Test status
Simulation time 243080323 ps
CPU time 0.98 seconds
Started Mar 10 01:38:25 PM PDT 24
Finished Mar 10 01:38:26 PM PDT 24
Peak memory 215732 kb
Host smart-79a9b457-2ab6-46ee-a459-efa9fb876778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901426876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2901426876
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1172463657
Short name T62
Test name
Test status
Simulation time 78796243 ps
CPU time 1.19 seconds
Started Mar 10 01:36:40 PM PDT 24
Finished Mar 10 01:36:42 PM PDT 24
Peak memory 214684 kb
Host smart-5b628e09-302e-4777-a234-e173cd9f6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172463657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1172463657
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.83423803
Short name T300
Test name
Test status
Simulation time 25878163 ps
CPU time 0.85 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 206100 kb
Host smart-4b49e5ce-b7e5-4f0d-9cc3-c83187f96e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83423803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.83423803
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2752260835
Short name T448
Test name
Test status
Simulation time 31462254 ps
CPU time 0.82 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 214900 kb
Host smart-5423bcc9-5d78-42ed-9f99-babd08ac23aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752260835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2752260835
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2168857003
Short name T335
Test name
Test status
Simulation time 93544436 ps
CPU time 1.08 seconds
Started Mar 10 01:36:34 PM PDT 24
Finished Mar 10 01:36:35 PM PDT 24
Peak memory 215364 kb
Host smart-d2b9b6c6-b840-465d-bda0-93e89665869a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168857003 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2168857003
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.142361056
Short name T108
Test name
Test status
Simulation time 23736542 ps
CPU time 1.1 seconds
Started Mar 10 01:36:35 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 222412 kb
Host smart-108ec64e-7530-4911-8240-b9199bac01d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142361056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.142361056
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2190098623
Short name T686
Test name
Test status
Simulation time 66217193 ps
CPU time 1.49 seconds
Started Mar 10 01:36:29 PM PDT 24
Finished Mar 10 01:36:30 PM PDT 24
Peak memory 218160 kb
Host smart-00a09fc3-36fc-4aaa-9771-82766f8a4dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190098623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2190098623
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3949497590
Short name T124
Test name
Test status
Simulation time 21423908 ps
CPU time 1.15 seconds
Started Mar 10 01:36:35 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 214784 kb
Host smart-5fac7039-f54a-4223-9e13-39bfc1ed142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949497590 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3949497590
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3532792547
Short name T564
Test name
Test status
Simulation time 48726651 ps
CPU time 0.95 seconds
Started Mar 10 01:36:30 PM PDT 24
Finished Mar 10 01:36:31 PM PDT 24
Peak memory 206196 kb
Host smart-93f711cf-b6c8-45a5-ac9d-24b2ae23cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532792547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3532792547
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1109361087
Short name T711
Test name
Test status
Simulation time 26846886 ps
CPU time 0.95 seconds
Started Mar 10 01:36:29 PM PDT 24
Finished Mar 10 01:36:30 PM PDT 24
Peak memory 214424 kb
Host smart-db64afab-40be-4b87-8f11-1f0a8cab8664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109361087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1109361087
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.188099509
Short name T775
Test name
Test status
Simulation time 382272036 ps
CPU time 4.03 seconds
Started Mar 10 01:36:33 PM PDT 24
Finished Mar 10 01:36:37 PM PDT 24
Peak memory 218288 kb
Host smart-75971ae2-8ea7-4b3a-8e79-7699bfd44ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188099509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.188099509
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3634209557
Short name T314
Test name
Test status
Simulation time 600925844790 ps
CPU time 1553.97 seconds
Started Mar 10 01:36:30 PM PDT 24
Finished Mar 10 02:02:24 PM PDT 24
Peak memory 221832 kb
Host smart-08d45a19-fef1-4877-b311-846b79751e58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634209557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3634209557
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.995852572
Short name T221
Test name
Test status
Simulation time 18446795 ps
CPU time 1.1 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 217236 kb
Host smart-03b66a85-17f7-41e8-bd2c-b3498bb16a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995852572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.995852572
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2950557022
Short name T554
Test name
Test status
Simulation time 128042519 ps
CPU time 2.48 seconds
Started Mar 10 01:38:25 PM PDT 24
Finished Mar 10 01:38:28 PM PDT 24
Peak memory 216120 kb
Host smart-5a2737c0-abbd-4e43-8bfe-3fcf46cd7406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950557022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2950557022
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2549477288
Short name T112
Test name
Test status
Simulation time 20330729 ps
CPU time 1.09 seconds
Started Mar 10 01:38:29 PM PDT 24
Finished Mar 10 01:38:32 PM PDT 24
Peak memory 217136 kb
Host smart-eeddacf1-7e40-4074-9354-c4bd7cbde16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549477288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2549477288
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2711284200
Short name T682
Test name
Test status
Simulation time 77455602 ps
CPU time 1.03 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:26 PM PDT 24
Peak memory 215492 kb
Host smart-6e6343bc-7cdc-4877-af59-b414df4f589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711284200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2711284200
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1516206919
Short name T4
Test name
Test status
Simulation time 94526039 ps
CPU time 0.81 seconds
Started Mar 10 01:38:29 PM PDT 24
Finished Mar 10 01:38:30 PM PDT 24
Peak memory 216932 kb
Host smart-849c9423-7fbe-451f-8dd4-02797bd120ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516206919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1516206919
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.938283991
Short name T338
Test name
Test status
Simulation time 87672866 ps
CPU time 1.4 seconds
Started Mar 10 01:38:23 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 216940 kb
Host smart-a3ef9217-b786-4ce4-8993-ad938f090d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938283991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.938283991
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.4085568571
Short name T779
Test name
Test status
Simulation time 23045813 ps
CPU time 1.17 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 217220 kb
Host smart-b807b055-5294-42da-a455-be35e69a948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085568571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4085568571
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2065972299
Short name T812
Test name
Test status
Simulation time 55143629 ps
CPU time 1.59 seconds
Started Mar 10 01:38:29 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 216536 kb
Host smart-a43718de-f3a9-4ac5-b787-7a8ba2776d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065972299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2065972299
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3916379101
Short name T743
Test name
Test status
Simulation time 17729363 ps
CPU time 1.08 seconds
Started Mar 10 01:38:31 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 217100 kb
Host smart-b5984f1e-7bb1-414f-8152-c2ff8059f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916379101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3916379101
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.254452096
Short name T526
Test name
Test status
Simulation time 53651458 ps
CPU time 1.92 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:26 PM PDT 24
Peak memory 217772 kb
Host smart-02fe8b7f-7d53-42e4-800a-2c772b41e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254452096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.254452096
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2908700351
Short name T618
Test name
Test status
Simulation time 30813314 ps
CPU time 0.87 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:30 PM PDT 24
Peak memory 217256 kb
Host smart-8e998f5f-6818-4b46-a778-6ac92ff73527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908700351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2908700351
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.45475695
Short name T749
Test name
Test status
Simulation time 65000989 ps
CPU time 1.12 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 215632 kb
Host smart-9537203d-9237-4cf7-809c-3dbd16d010ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45475695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.45475695
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3791021753
Short name T790
Test name
Test status
Simulation time 71409196 ps
CPU time 1.15 seconds
Started Mar 10 01:38:24 PM PDT 24
Finished Mar 10 01:38:25 PM PDT 24
Peak memory 218312 kb
Host smart-01699980-a90e-4f6b-967f-c25c73007fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791021753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3791021753
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2623695868
Short name T479
Test name
Test status
Simulation time 55256727 ps
CPU time 1.26 seconds
Started Mar 10 01:38:23 PM PDT 24
Finished Mar 10 01:38:24 PM PDT 24
Peak memory 217000 kb
Host smart-3f4237fb-1b83-4f22-946f-111c4fe631bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623695868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2623695868
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2879461182
Short name T157
Test name
Test status
Simulation time 138898235 ps
CPU time 1.34 seconds
Started Mar 10 01:38:35 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 231472 kb
Host smart-0880cf45-c558-4fac-89bc-553f00d4da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879461182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2879461182
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.118877663
Short name T54
Test name
Test status
Simulation time 32927467 ps
CPU time 1.33 seconds
Started Mar 10 01:38:26 PM PDT 24
Finished Mar 10 01:38:28 PM PDT 24
Peak memory 217952 kb
Host smart-4b2e98a6-5eec-4b19-a003-adacefd1237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118877663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.118877663
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1210907353
Short name T65
Test name
Test status
Simulation time 25753913 ps
CPU time 1.2 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:30 PM PDT 24
Peak memory 219200 kb
Host smart-6c3abe9d-7c58-45cc-8465-1358fd812a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210907353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1210907353
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1252779448
Short name T728
Test name
Test status
Simulation time 32910834 ps
CPU time 1.4 seconds
Started Mar 10 01:38:27 PM PDT 24
Finished Mar 10 01:38:30 PM PDT 24
Peak memory 217020 kb
Host smart-588af052-510a-478c-9a3b-2934af2eb9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252779448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1252779448
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.557607505
Short name T71
Test name
Test status
Simulation time 27860465 ps
CPU time 1.2 seconds
Started Mar 10 01:38:28 PM PDT 24
Finished Mar 10 01:38:31 PM PDT 24
Peak memory 219204 kb
Host smart-ef575d4c-563a-497a-bbe8-385d11ad2676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557607505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.557607505
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1196145130
Short name T499
Test name
Test status
Simulation time 53122979 ps
CPU time 1.39 seconds
Started Mar 10 01:38:35 PM PDT 24
Finished Mar 10 01:38:37 PM PDT 24
Peak memory 216748 kb
Host smart-03b20637-0844-4e27-9a02-90e3e1e1127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196145130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1196145130
Directory /workspace/99.edn_genbits/latest
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