Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	672784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5588473

1

T1

7

T2

24

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1648270	1			T1	20		T2	81		T3	1
values[0x0]	2134278	1			T1	6		T2	14		T3	5
values[0x1]	2478709	1			T1	4		T2	7		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5931995

1

T1

15

T2

48

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24017	1			T2	1		T6	1		T4	1
valid_sources[0x01]	22844	1			T4	5		T37	2		T24	188
valid_sources[0x02]	21534	1			T2	2		T6	2		T4	4
valid_sources[0x03]	22660	1			T2	1		T6	2		T4	1
valid_sources[0x04]	23063	1			T2	2		T6	1		T4	5
valid_sources[0x05]	22757	1			T6	1		T4	4		T10	1
valid_sources[0x06]	25860	1			T4	5		T37	2		T18	1
valid_sources[0x07]	23305	1			T6	1		T4	13		T10	5
valid_sources[0x08]	24692	1			T4	3		T37	5		T12	1
valid_sources[0x09]	23629	1			T3	1		T4	3		T37	6
valid_sources[0x0a]	24725	1			T2	1		T6	1		T4	6
valid_sources[0x0b]	25378	1			T4	1		T10	1		T24	145
valid_sources[0x0c]	23464	1			T6	1		T4	3		T12	1
valid_sources[0x0d]	24931	1			T6	2		T4	7		T12	1
valid_sources[0x0e]	25536	1			T6	3		T4	3		T18	1
valid_sources[0x0f]	24620	1			T6	3		T4	2		T12	1
valid_sources[0x10]	24076	1			T2	2		T6	1		T4	2
valid_sources[0x11]	23831	1			T6	2		T4	5		T18	1
valid_sources[0x12]	23583	1			T6	1		T4	2		T30	2
valid_sources[0x13]	23803	1			T2	1		T4	3		T10	1
valid_sources[0x14]	23777	1			T4	6		T30	1		T24	170
valid_sources[0x15]	21581	1			T2	1		T12	1		T24	196
valid_sources[0x16]	24759	1			T2	1		T6	1		T4	3
valid_sources[0x17]	26404	1			T2	1		T6	1		T4	5
valid_sources[0x18]	24974	1			T4	3		T24	167		T25	610
valid_sources[0x19]	24393	1			T4	3		T10	3		T11	1
valid_sources[0x1a]	27234	1			T6	1		T4	1		T10	1
valid_sources[0x1b]	24082	1			T2	1		T4	3		T10	2
valid_sources[0x1c]	23596	1			T2	2		T4	5		T10	2
valid_sources[0x1d]	22820	1			T2	1		T3	1		T6	1
valid_sources[0x1e]	24809	1			T2	1		T6	3		T4	8
valid_sources[0x1f]	25328	1			T4	2		T11	1		T12	1
valid_sources[0x20]	25028	1			T4	4		T24	221		T25	604
valid_sources[0x21]	24908	1			T1	1		T4	10		T18	2
valid_sources[0x22]	23930	1			T6	2		T4	7		T18	1
valid_sources[0x23]	23476	1			T6	2		T4	1		T24	197
valid_sources[0x24]	25406	1			T6	1		T4	1		T10	3
valid_sources[0x25]	23142	1			T6	3		T4	5		T18	2
valid_sources[0x26]	25920	1			T6	2		T4	2		T24	154
valid_sources[0x27]	24367	1			T1	2		T2	1		T4	2
valid_sources[0x28]	23123	1			T4	1		T37	9		T12	1
valid_sources[0x29]	27722	1			T2	1		T4	4		T37	1
valid_sources[0x2a]	25828	1			T6	1		T4	1		T30	1
valid_sources[0x2b]	25968	1			T4	7		T12	1		T24	176
valid_sources[0x2c]	23511	1			T2	2		T4	5		T18	2
valid_sources[0x2d]	24218	1			T6	1		T4	5		T18	1
valid_sources[0x2e]	24722	1			T4	8		T24	184		T25	560
valid_sources[0x2f]	25567	1			T6	1		T4	4		T10	1
valid_sources[0x30]	24328	1			T4	9		T24	186		T25	593
valid_sources[0x31]	24784	1			T2	2		T6	1		T4	1
valid_sources[0x32]	24814	1			T6	3		T4	1		T24	165
valid_sources[0x33]	24388	1			T4	4		T18	1		T24	182
valid_sources[0x34]	23052	1			T2	1		T6	1		T4	5
valid_sources[0x35]	25263	1			T2	2		T4	7		T10	2
valid_sources[0x36]	22391	1			T6	1		T4	1		T18	1
valid_sources[0x37]	22612	1			T4	8		T24	208		T25	604
valid_sources[0x38]	23947	1			T4	8		T24	171		T25	573
valid_sources[0x39]	24614	1			T6	3		T4	4		T37	1
valid_sources[0x3a]	25200	1			T2	1		T6	3		T4	3
valid_sources[0x3b]	24650	1			T4	1		T18	1		T24	161
valid_sources[0x3c]	25392	1			T3	2		T4	3		T10	1
valid_sources[0x3d]	21372	1			T2	1		T4	6		T18	1
valid_sources[0x3e]	24411	1			T6	4		T4	2		T24	142
valid_sources[0x3f]	25565	1			T2	2		T4	2		T30	1
valid_sources[0x40]	24559	1			T4	12		T24	212		T25	575
valid_sources[0x41]	24402	1			T2	1		T4	9		T30	2
valid_sources[0x42]	27055	1			T4	2		T10	1		T24	186
valid_sources[0x43]	24877	1			T4	5		T11	2		T18	1
valid_sources[0x44]	24353	1			T6	2		T4	4		T10	2
valid_sources[0x45]	24234	1			T6	2		T24	208		T25	596
valid_sources[0x46]	23689	1			T10	3		T12	1		T24	183
valid_sources[0x47]	25556	1			T24	182		T25	585		T29	2
valid_sources[0x48]	25618	1			T4	4		T24	192		T25	580
valid_sources[0x49]	24218	1			T1	3		T4	2		T18	2
valid_sources[0x4a]	22882	1			T4	6		T11	1		T18	3
valid_sources[0x4b]	24518	1			T4	2		T12	3		T24	170
valid_sources[0x4c]	24890	1			T1	1		T2	1		T6	3
valid_sources[0x4d]	25037	1			T6	2		T4	3		T10	2
valid_sources[0x4e]	24222	1			T4	3		T24	167		T25	618
valid_sources[0x4f]	23746	1			T6	1		T4	8		T37	1
valid_sources[0x50]	25304	1			T4	2		T10	5		T24	203
valid_sources[0x51]	23156	1			T4	3		T10	1		T30	2
valid_sources[0x52]	22298	1			T2	2		T4	3		T24	207
valid_sources[0x53]	24340	1			T2	1		T6	3		T4	2
valid_sources[0x54]	24473	1			T4	11		T30	1		T24	192
valid_sources[0x55]	24734	1			T2	3		T6	2		T4	8
valid_sources[0x56]	24623	1			T4	5		T10	1		T30	2
valid_sources[0x57]	26778	1			T2	1		T4	7		T11	2
valid_sources[0x58]	26003	1			T1	8		T4	1		T30	1
valid_sources[0x59]	26212	1			T2	1		T6	1		T4	8
valid_sources[0x5a]	24768	1			T6	3		T4	5		T18	1
valid_sources[0x5b]	25740	1			T4	7		T24	170		T25	570
valid_sources[0x5c]	25223	1			T4	9		T11	1		T18	2
valid_sources[0x5d]	26044	1			T2	1		T12	1		T24	178
valid_sources[0x5e]	23566	1			T4	10		T11	3		T30	2
valid_sources[0x5f]	25691	1			T6	1		T4	8		T12	1
valid_sources[0x60]	22350	1			T2	1		T6	1		T4	6
valid_sources[0x61]	24493	1			T4	8		T10	2		T11	1
valid_sources[0x62]	25405	1			T2	2		T4	2		T10	2
valid_sources[0x63]	21465	1			T6	2		T4	1		T12	1
valid_sources[0x64]	23059	1			T2	3		T4	6		T12	1
valid_sources[0x65]	24347	1			T2	1		T4	11		T37	2
valid_sources[0x66]	25369	1			T3	2		T4	4		T12	2
valid_sources[0x67]	24172	1			T4	2		T24	192		T25	618
valid_sources[0x68]	23133	1			T4	2		T11	1		T24	202
valid_sources[0x69]	23503	1			T2	1		T3	1		T4	8
valid_sources[0x6a]	24698	1			T4	8		T12	1		T18	1
valid_sources[0x6b]	23838	1			T2	3		T6	1		T4	6
valid_sources[0x6c]	26846	1			T6	2		T4	6		T18	1
valid_sources[0x6d]	25366	1			T4	4		T18	2		T24	179
valid_sources[0x6e]	26464	1			T6	1		T4	12		T11	1
valid_sources[0x6f]	23745	1			T4	4		T18	2		T24	193
valid_sources[0x70]	23100	1			T6	1		T4	7		T30	2
valid_sources[0x71]	24333	1			T2	1		T4	2		T18	1
valid_sources[0x72]	25725	1			T4	7		T24	180		T25	557
valid_sources[0x73]	23385	1			T37	1		T11	3		T24	251
valid_sources[0x74]	22228	1			T4	1		T24	200		T25	573
valid_sources[0x75]	25338	1			T2	3		T4	9		T24	185
valid_sources[0x76]	26099	1			T2	4		T6	2		T4	7
valid_sources[0x77]	26120	1			T4	6		T24	177		T25	612
valid_sources[0x78]	24005	1			T6	1		T4	4		T18	1
valid_sources[0x79]	26334	1			T2	1		T6	3		T4	4
valid_sources[0x7a]	24666	1			T4	9		T10	3		T37	2
valid_sources[0x7b]	24679	1			T6	1		T4	9		T24	212
valid_sources[0x7c]	26252	1			T1	4		T6	4		T4	3
valid_sources[0x7d]	25511	1			T6	2		T4	13		T24	243
valid_sources[0x7e]	25688	1			T2	1		T6	2		T4	10
valid_sources[0x7f]	24596	1			T6	3		T4	3		T11	1
valid_sources[0x80]	24907	1			T4	5		T12	1		T24	166

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1407043

1

T1

2

T2

7

T6

6

values[0x0]

all_enables

biggest_size

2092319

1

T1

4

T2

11

T3

2

values[0x1]

all_enables

biggest_size

2089111

1

T1

1

T2

6

T3

4