Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2564	1			T6	1		T4	9		T10	1
non_zero_bins[1]	1750	1			T2	1		T6	1		T4	5
zero	8039	1			T1	2		T2	4		T6	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	511	1			T4	4		T30	1		T24	7
uni	3480	1			T2	2		T6	3		T4	13
gen	3653	1			T1	1		T2	1		T6	2
res	726	1			T4	1		T10	1		T11	2
ins	3983	1			T1	1		T2	2		T6	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8364

1

T1

2

T2

2

T6

5

mubi_true

3989

1

T2

3

T6

3

T4

11

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T12

1

T18

1

T19

1

pass

12303

1

T1

2

T2

5

T6

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	113	1			T4	1		T24	1		T33	1
upd	non_zero_bins[0]	pass	mubi_true	148	1			T4	2		T24	2		T25	1
upd	non_zero_bins[1]	pass	mubi_false	73	1			T24	2		T25	2		T147	1
upd	non_zero_bins[1]	pass	mubi_true	78	1			T24	1		T25	2		T148	1
upd	zero	pass	mubi_false	49	1			T4	1		T30	1		T34	1
upd	zero	pass	mubi_true	50	1			T24	1		T145	1		T233	1
uni	zero	fail	mubi_false	9	1			T122	1		T123	1		T124	1
uni	zero	pass	mubi_false	2545	1			T2	1		T6	3		T4	8
uni	zero	pass	mubi_true	926	1			T2	1		T4	5		T24	14
gen	non_zero_bins[0]	pass	mubi_false	470	1			T4	3		T11	1		T30	1
gen	non_zero_bins[0]	pass	mubi_true	444	1			T27	1		T28	1		T24	6
gen	non_zero_bins[1]	pass	mubi_false	326	1			T4	1		T24	1		T25	3
gen	non_zero_bins[1]	pass	mubi_true	315	1			T4	1		T24	5		T25	2
gen	zero	fail	mubi_false	19	1			T18	1		T19	1		T48	1
gen	zero	pass	mubi_false	1696	1			T1	1		T4	8		T11	3
gen	zero	pass	mubi_true	383	1			T2	1		T6	2		T37	1
res	non_zero_bins[0]	pass	mubi_false	158	1			T4	1		T11	2		T24	1
res	non_zero_bins[0]	pass	mubi_true	179	1			T24	1		T25	2		T13	2
res	non_zero_bins[1]	pass	mubi_false	109	1			T27	1		T24	4		T25	2
res	non_zero_bins[1]	pass	mubi_true	118	1			T10	1		T24	2		T25	1
res	zero	fail	mubi_false	10	1			T12	1		T149	1		T150	1
res	zero	pass	mubi_false	76	1			T24	2		T25	1		T143	1
res	zero	pass	mubi_true	76	1			T28	1		T24	1		T189	1
ins	non_zero_bins[0]	pass	mubi_false	539	1			T4	1		T10	1		T37	2
ins	non_zero_bins[0]	pass	mubi_true	513	1			T6	1		T4	1		T24	5
ins	non_zero_bins[1]	pass	mubi_false	373	1			T2	1		T6	1		T4	1
ins	non_zero_bins[1]	pass	mubi_true	358	1			T4	2		T24	5		T25	4
ins	zero	fail	mubi_false	8	1			T108	1		T109	1		T234	1
ins	zero	fail	mubi_true	4	1			T110	1		T235	1		T236	1
ins	zero	pass	mubi_false	1791	1			T1	1		T6	1		T4	8
ins	zero	pass	mubi_true	397	1			T2	1		T12	1		T18	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded