Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218252999	9907754	0	0
boot_gen_cmd_rd_A	218252999	63817	0	0
boot_ins_cmd_rd_A	218252999	72384	0	0
ctrl_rd_A	218252999	63803	0	0
err_code_test_rd_A	218252999	72535	0	0
intr_enable_rd_A	218252999	71659	0	0
max_num_reqs_between_reseeds_rd_A	218252999	63674	0	0
regwen_rd_A	218252999	74974	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	9907754	0	0
T23	1092	0	0	0
T24	196967	80615	0	0
T25	604182	252546	0	0
T26	0	77364	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T34	3985	0	0	0
T35	5211	0	0	0
T108	1623	0	0	0
T128	1645	0	0	0
T144	837	0	0	0
T188	0	187064	0	0
T189	0	249103	0	0
T190	0	180489	0	0
T191	0	87698	0	0
T192	0	99518	0	0
T193	0	111245	0	0
T194	0	136139	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	63817	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2293	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T59	0	4147	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	5577	0	0
T189	0	3784	0	0
T191	0	2348	0	0
T194	0	2154	0	0
T195	0	3666	0	0
T196	0	8445	0	0
T197	0	5665	0	0
T198	0	3326	0	0
T199	3896	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	72384	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2612	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T59	0	4989	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	6458	0	0
T189	0	4245	0	0
T191	0	2801	0	0
T194	0	2342	0	0
T195	0	4179	0	0
T196	0	9346	0	0
T197	0	6350	0	0
T198	0	3535	0	0
T199	3896	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	63803	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2424	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	5684	0	0
T189	0	3821	0	0
T191	0	2461	0	0
T194	0	1985	0	0
T195	0	3369	0	0
T199	3896	0	0	0
T200	0	9	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	72535	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2394	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T59	0	4971	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	6293	0	0
T189	0	4278	0	0
T191	0	2827	0	0
T194	0	2573	0	0
T195	0	3827	0	0
T196	0	9483	0	0
T197	0	6500	0	0
T198	0	3720	0	0
T199	3896	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	71659	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2391	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T64	678	0	0	0
T65	849	0	0	0
T147	0	133	0	0
T188	0	6074	0	0
T189	0	4179	0	0
T191	0	2967	0	0
T194	0	2478	0	0
T199	3896	0	0	0
T201	0	63	0	0
T203	0	74	0	0
T204	0	34	0	0
T205	0	13	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	63674	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2397	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T59	0	4545	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	5632	0	0
T189	0	3526	0	0
T191	0	2480	0	0
T194	0	1900	0	0
T195	0	3058	0	0
T196	0	8316	0	0
T197	0	5614	0	0
T198	0	3023	0	0
T199	3896	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218252999	74974	0	0
T13	2480	0	0	0
T16	807	0	0	0
T26	229514	2620	0	0
T45	2032	0	0	0
T46	1847	0	0	0
T47	2705	0	0	0
T48	2399	0	0	0
T59	0	5147	0	0
T64	678	0	0	0
T65	849	0	0	0
T188	0	6392	0	0
T189	0	4314	0	0
T191	0	2781	0	0
T194	0	2578	0	0
T195	0	4059	0	0
T196	0	9771	0	0
T197	0	6451	0	0
T198	0	3635	0	0
T199	3896	0	0	0