Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T119,T121,T153
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T107,T154,T155
DataWait->Error	99	Covered	T16,T67,T7
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T23,T64

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T2,T4,T10
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T5,T64,T65

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1524264084	824053	0	0
FpvSecCmErrorStEscalate_A	1524264084	829352	0	0
u_state_regs_A	1524233479	1523205207	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1524264084	824053	0	0
T5	4585	1721	0	0
T7	0	2765	0	0
T16	0	2765	0	0
T17	0	2569	0	0
T19	18907	0	0	0
T23	7644	4270	0	0
T24	1378769	0	0	0
T25	4229274	0	0	0
T28	16205	0	0	0
T29	26096	0	0	0
T33	9240	0	0	0
T64	0	2190	0	0
T65	0	3030	0	0
T67	0	7973	0	0
T102	0	4857	0	0
T108	11361	0	0	0
T125	0	2386	0	0
T128	11515	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1524264084	829352	0	0
T5	4585	1728	0	0
T7	0	2772	0	0
T16	0	2772	0	0
T17	0	2576	0	0
T19	18907	0	0	0
T23	7644	4277	0	0
T24	1378769	0	0	0
T25	4229274	0	0	0
T28	16205	0	0	0
T29	26096	0	0	0
T33	9240	0	0	0
T64	0	2197	0	0
T65	0	3037	0	0
T67	0	7980	0	0
T102	0	4864	0	0
T108	11361	0	0	0
T125	0	2393	0	0
T128	11515	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1524233479	1523205207	0	0
T1	7651	6622	0	0
T2	12929	12530	0	0
T3	11522	11025	0	0
T4	211176	205016	0	0
T6	28819	28364	0	0
T10	27839	27307	0	0
T11	18774	18368	0	0
T12	18802	18361	0	0
T18	16058	15687	0	0
T37	9079	8421	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T157,T158,T159
DataWait->Error	99	Covered	T16,T67,T7
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T160,T20,T161
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T23,T17,T127

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T2,T4,T37
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T5,T64,T65

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	115579	0	0
FpvSecCmErrorStEscalate_A	217752012	116336	0	0
u_state_regs_A	217721407	217574511	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	115579	0	0
T5	655	203	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	270	0	0
T65	0	390	0	0
T67	0	1139	0	0
T102	0	651	0	0
T108	1623	0	0	0
T125	0	298	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	116336	0	0
T5	655	204	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	271	0	0
T65	0	391	0	0
T67	0	1140	0	0
T102	0	652	0	0
T108	1623	0	0	0
T125	0	299	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217721407	217574511	0	0
T1	1045	898	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T27,T28
DataWait	75	Covered	T2,T27,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T27,T28
DataWait->AckPls	80	Covered	T2,T27,T28
DataWait->Disabled	107	Covered	T112,T90,T162
DataWait->Error	99	Covered	T40,T163,T164
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T2,T27,T28
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T23,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T2,T27,T28
Idle	-	1	0	-	Covered	T2,T27,T28
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T2,T27,T28
DataWait	-	-	-	0	Covered	T2,T27,T28
AckPls	-	-	-	-	Covered	T2,T27,T28
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T10,T27
DataWait	75	Covered	T2,T10,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T10,T27
DataWait->AckPls	80	Covered	T2,T10,T27
DataWait->Disabled	107	Covered	T107,T165,T166
DataWait->Error	99	Covered	T82
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T2,T10,T27
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T23,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T2,T10,T27
Idle	-	1	0	-	Covered	T2,T10,T27
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T2,T10,T27
DataWait	-	-	-	0	Covered	T2,T10,T27
AckPls	-	-	-	-	Covered	T2,T10,T27
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T27,T29
DataWait	75	Covered	T6,T27,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T27,T29
DataWait->AckPls	80	Covered	T6,T27,T29
DataWait->Disabled	107	Covered	T155,T111,T167
DataWait->Error	99	Covered	T168,T169,T170
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T27,T29
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T23,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T27,T29
Idle	-	1	0	-	Covered	T6,T27,T29
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T27,T29
DataWait	-	-	-	0	Covered	T6,T27,T29
AckPls	-	-	-	-	Covered	T6,T27,T29
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T11,T12
DataWait	75	Covered	T6,T11,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T153
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T11,T12
DataWait->AckPls	80	Covered	T6,T11,T12
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T23,T38,T56
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T11,T12
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T64,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T11,T12
Idle	-	1	0	-	Covered	T6,T11,T12
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T11,T12
DataWait	-	-	-	0	Covered	T6,T11,T27
AckPls	-	-	-	-	Covered	T6,T11,T12
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T27,T28
DataWait	75	Covered	T6,T27,T5
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T119,T171
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T27,T28
DataWait->AckPls	80	Covered	T6,T27,T28
DataWait->Disabled	107	Covered	T154,T172,T113
DataWait->Error	99	Covered	T5,T43,T71
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T27,T5
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T23,T64,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T27,T28
Idle	-	1	0	-	Covered	T6,T27,T5
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T27,T28
DataWait	-	-	-	0	Covered	T6,T27,T5
AckPls	-	-	-	-	Covered	T6,T27,T28
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T10,T12
DataWait	75	Covered	T6,T10,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T6
Error	99	Covered	T5,T23,T64
Idle	68	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T121,T173
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T10,T12
DataWait->AckPls	80	Covered	T6,T10,T12
DataWait->Disabled	107	Covered	T10,T75,T174
DataWait->Error	99	Covered	T175
Disabled->EndPointClear	63	Covered	T1,T2,T6
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T116,T156,T117
EndPointClear->Error	99	Covered	T103,T9,T87
EndPointClear->Idle	68	Covered	T1,T2,T6
Idle->DataWait	75	Covered	T6,T10,T12
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T5,T23,T64

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T6
Idle	-	1	1	-	Covered	T6,T10,T12
Idle	-	1	0	-	Covered	T6,T10,T12
Idle	-	0	-	-	Covered	T1,T2,T6
DataWait	-	-	-	1	Covered	T6,T10,T12
DataWait	-	-	-	0	Covered	T6,T10,T12
AckPls	-	-	-	-	Covered	T6,T10,T12
Error	-	-	-	-	Covered	T5,T23,T64
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T23,T64
0	1	Covered	T1,T10,T12
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217752012	118079	0	0
FpvSecCmErrorStEscalate_A	217752012	118836	0	0
u_state_regs_A	217752012	217605116	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118079	0	0
T5	655	253	0	0
T7	0	395	0	0
T16	0	395	0	0
T17	0	367	0	0
T19	2701	0	0	0
T23	1092	610	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	320	0	0
T65	0	440	0	0
T67	0	1139	0	0
T102	0	701	0	0
T108	1623	0	0	0
T125	0	348	0	0
T128	1645	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	118836	0	0
T5	655	254	0	0
T7	0	396	0	0
T16	0	396	0	0
T17	0	368	0	0
T19	2701	0	0	0
T23	1092	611	0	0
T24	196967	0	0	0
T25	604182	0	0	0
T28	2315	0	0	0
T29	3728	0	0	0
T33	1320	0	0	0
T64	0	321	0	0
T65	0	441	0	0
T67	0	1140	0	0
T102	0	702	0	0
T108	1623	0	0	0
T125	0	349	0	0
T128	1645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217752012	217605116	0	0
T1	1101	954	0	0
T2	1847	1790	0	0
T3	1646	1575	0	0
T4	30168	29288	0	0
T6	4117	4052	0	0
T10	3977	3901	0	0
T11	2682	2624	0	0
T12	2686	2623	0	0
T18	2294	2241	0	0
T37	1297	1203	0	0