Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 26 | 23 | 88.46 |
Logical | 26 | 23 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T18 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T10,T11,T13 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T10,T11,T13 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T136 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T133,T135 |
1 | 0 | 1 | Covered | T10,T11,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T10,T11,T12 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T18 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T10,T11,T12 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T10,T11,T18 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T10,T11,T13 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T11,T12 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
435170788 |
876635 |
0 |
0 |
T5 |
246 |
0 |
0 |
0 |
T7 |
0 |
292 |
0 |
0 |
T10 |
7954 |
6375 |
0 |
0 |
T11 |
5364 |
2333 |
0 |
0 |
T12 |
5372 |
600 |
0 |
0 |
T13 |
0 |
1524 |
0 |
0 |
T18 |
4588 |
664 |
0 |
0 |
T27 |
3302 |
0 |
0 |
0 |
T28 |
4630 |
0 |
0 |
0 |
T30 |
4194 |
0 |
0 |
0 |
T36 |
2414 |
0 |
0 |
0 |
T37 |
2594 |
0 |
0 |
0 |
T46 |
0 |
1345 |
0 |
0 |
T49 |
0 |
1842 |
0 |
0 |
T52 |
0 |
2704 |
0 |
0 |
T137 |
0 |
434653 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
435504024 |
435210232 |
0 |
0 |
T1 |
2202 |
1908 |
0 |
0 |
T2 |
3694 |
3580 |
0 |
0 |
T3 |
3292 |
3150 |
0 |
0 |
T4 |
60336 |
58576 |
0 |
0 |
T6 |
8234 |
8104 |
0 |
0 |
T10 |
7954 |
7802 |
0 |
0 |
T11 |
5364 |
5248 |
0 |
0 |
T12 |
5372 |
5246 |
0 |
0 |
T18 |
4588 |
4482 |
0 |
0 |
T37 |
2594 |
2406 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
435504024 |
435210232 |
0 |
0 |
T1 |
2202 |
1908 |
0 |
0 |
T2 |
3694 |
3580 |
0 |
0 |
T3 |
3292 |
3150 |
0 |
0 |
T4 |
60336 |
58576 |
0 |
0 |
T6 |
8234 |
8104 |
0 |
0 |
T10 |
7954 |
7802 |
0 |
0 |
T11 |
5364 |
5248 |
0 |
0 |
T12 |
5372 |
5246 |
0 |
0 |
T18 |
4588 |
4482 |
0 |
0 |
T37 |
2594 |
2406 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
435504024 |
435210232 |
0 |
0 |
T1 |
2202 |
1908 |
0 |
0 |
T2 |
3694 |
3580 |
0 |
0 |
T3 |
3292 |
3150 |
0 |
0 |
T4 |
60336 |
58576 |
0 |
0 |
T6 |
8234 |
8104 |
0 |
0 |
T10 |
7954 |
7802 |
0 |
0 |
T11 |
5364 |
5248 |
0 |
0 |
T12 |
5372 |
5246 |
0 |
0 |
T18 |
4588 |
4482 |
0 |
0 |
T37 |
2594 |
2406 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
435504024 |
948398 |
0 |
0 |
T5 |
1310 |
386 |
0 |
0 |
T10 |
7954 |
6375 |
0 |
0 |
T11 |
5364 |
2333 |
0 |
0 |
T12 |
5372 |
600 |
0 |
0 |
T13 |
0 |
1524 |
0 |
0 |
T16 |
0 |
355 |
0 |
0 |
T18 |
4588 |
664 |
0 |
0 |
T23 |
0 |
296 |
0 |
0 |
T27 |
3302 |
0 |
0 |
0 |
T28 |
4630 |
0 |
0 |
0 |
T30 |
4194 |
0 |
0 |
0 |
T36 |
2414 |
0 |
0 |
0 |
T37 |
2594 |
0 |
0 |
0 |
T64 |
0 |
296 |
0 |
0 |
T65 |
0 |
310 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
Conditions | 26 | 22 | 84.62 |
Logical | 26 | 22 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T18 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T13,T46,T49 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T13,T46,T49 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T133,T135,T138 |
1 | 0 | 1 | Covered | T10,T11,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T10,T11,T12 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T18 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T10,T11,T12 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T10,T11,T18 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T13,T46,T49 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T11,T12 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217585394 |
442371 |
0 |
0 |
T5 |
123 |
0 |
0 |
0 |
T7 |
0 |
184 |
0 |
0 |
T10 |
3977 |
3232 |
0 |
0 |
T11 |
2682 |
1199 |
0 |
0 |
T12 |
2686 |
297 |
0 |
0 |
T13 |
0 |
767 |
0 |
0 |
T18 |
2294 |
332 |
0 |
0 |
T27 |
1651 |
0 |
0 |
0 |
T28 |
2315 |
0 |
0 |
0 |
T30 |
2097 |
0 |
0 |
0 |
T36 |
1207 |
0 |
0 |
0 |
T37 |
1297 |
0 |
0 |
0 |
T46 |
0 |
679 |
0 |
0 |
T49 |
0 |
931 |
0 |
0 |
T52 |
0 |
1353 |
0 |
0 |
T137 |
0 |
217364 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
478501 |
0 |
0 |
T5 |
655 |
191 |
0 |
0 |
T10 |
3977 |
3232 |
0 |
0 |
T11 |
2682 |
1199 |
0 |
0 |
T12 |
2686 |
297 |
0 |
0 |
T13 |
0 |
767 |
0 |
0 |
T16 |
0 |
176 |
0 |
0 |
T18 |
2294 |
332 |
0 |
0 |
T23 |
0 |
147 |
0 |
0 |
T27 |
1651 |
0 |
0 |
0 |
T28 |
2315 |
0 |
0 |
0 |
T30 |
2097 |
0 |
0 |
0 |
T36 |
1207 |
0 |
0 |
0 |
T37 |
1297 |
0 |
0 |
0 |
T64 |
0 |
147 |
0 |
0 |
T65 |
0 |
154 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
Conditions | 26 | 23 | 88.46 |
Logical | 26 | 23 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T49,T52,T136 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T10,T11,T13 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T10,T11,T13 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T136 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T139,T140 |
1 | 0 | 1 | Covered | T10,T11,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T10,T11,T12 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T49,T52,T136 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T10,T11,T12 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T49,T52,T136 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T10,T11,T12 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T49,T52,T136 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T10,T11,T13 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T10,T11,T12 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T11,T12 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217585394 |
434264 |
0 |
0 |
T5 |
123 |
0 |
0 |
0 |
T7 |
0 |
108 |
0 |
0 |
T10 |
3977 |
3143 |
0 |
0 |
T11 |
2682 |
1134 |
0 |
0 |
T12 |
2686 |
303 |
0 |
0 |
T13 |
0 |
757 |
0 |
0 |
T18 |
2294 |
332 |
0 |
0 |
T27 |
1651 |
0 |
0 |
0 |
T28 |
2315 |
0 |
0 |
0 |
T30 |
2097 |
0 |
0 |
0 |
T36 |
1207 |
0 |
0 |
0 |
T37 |
1297 |
0 |
0 |
0 |
T46 |
0 |
666 |
0 |
0 |
T49 |
0 |
911 |
0 |
0 |
T52 |
0 |
1351 |
0 |
0 |
T137 |
0 |
217289 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
217605116 |
0 |
0 |
T1 |
1101 |
954 |
0 |
0 |
T2 |
1847 |
1790 |
0 |
0 |
T3 |
1646 |
1575 |
0 |
0 |
T4 |
30168 |
29288 |
0 |
0 |
T6 |
4117 |
4052 |
0 |
0 |
T10 |
3977 |
3901 |
0 |
0 |
T11 |
2682 |
2624 |
0 |
0 |
T12 |
2686 |
2623 |
0 |
0 |
T18 |
2294 |
2241 |
0 |
0 |
T37 |
1297 |
1203 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217752012 |
469897 |
0 |
0 |
T5 |
655 |
195 |
0 |
0 |
T10 |
3977 |
3143 |
0 |
0 |
T11 |
2682 |
1134 |
0 |
0 |
T12 |
2686 |
303 |
0 |
0 |
T13 |
0 |
757 |
0 |
0 |
T16 |
0 |
179 |
0 |
0 |
T18 |
2294 |
332 |
0 |
0 |
T23 |
0 |
149 |
0 |
0 |
T27 |
1651 |
0 |
0 |
0 |
T28 |
2315 |
0 |
0 |
0 |
T30 |
2097 |
0 |
0 |
0 |
T36 |
1207 |
0 |
0 |
0 |
T37 |
1297 |
0 |
0 |
0 |
T64 |
0 |
149 |
0 |
0 |
T65 |
0 |
156 |
0 |
0 |