Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	697969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5775370

1

T1

29

T2

23

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1703501	1			T1	41		T2	107		T3	4
values[0x0]	2205588	1			T1	12		T2	12		T3	2
values[0x1]	2564250	1			T1	14		T2	11		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	341117	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6132222

1

T1

40

T2

64

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26344	1			T41	1		T27	642		T11	1
valid_sources[0x01]	24850	1			T37	3		T41	5		T10	1
valid_sources[0x02]	25086	1			T32	3		T41	2		T27	574
valid_sources[0x03]	25889	1			T41	3		T10	1		T27	689
valid_sources[0x04]	24954	1			T30	1		T10	2		T35	2
valid_sources[0x05]	24339	1			T2	1		T26	1		T5	4
valid_sources[0x06]	25470	1			T2	1		T5	2		T30	3
valid_sources[0x07]	25211	1			T2	1		T5	2		T33	1
valid_sources[0x08]	25113	1			T1	1		T33	1		T10	1
valid_sources[0x09]	24793	1			T5	4		T41	3		T35	1
valid_sources[0x0a]	25969	1			T2	1		T26	1		T5	3
valid_sources[0x0b]	25199	1			T2	1		T26	2		T5	2
valid_sources[0x0c]	25519	1			T41	1		T27	668		T11	1
valid_sources[0x0d]	24865	1			T2	1		T26	1		T41	3
valid_sources[0x0e]	25512	1			T5	2		T30	3		T41	1
valid_sources[0x0f]	26062	1			T1	2		T5	4		T27	613
valid_sources[0x10]	25619	1			T1	8		T2	2		T5	2
valid_sources[0x11]	25869	1			T32	1		T41	8		T35	1
valid_sources[0x12]	24958	1			T5	1		T33	1		T41	1
valid_sources[0x13]	25106	1			T1	5		T5	2		T30	2
valid_sources[0x14]	24527	1			T1	1		T2	3		T9	7
valid_sources[0x15]	25752	1			T2	1		T37	1		T10	3
valid_sources[0x16]	26696	1			T26	1		T5	3		T37	2
valid_sources[0x17]	25487	1			T1	1		T5	2		T37	1
valid_sources[0x18]	25528	1			T2	1		T30	1		T41	1
valid_sources[0x19]	24215	1			T2	1		T5	1		T30	3
valid_sources[0x1a]	24609	1			T5	3		T37	1		T41	7
valid_sources[0x1b]	26110	1			T5	2		T30	2		T41	1
valid_sources[0x1c]	25334	1			T2	1		T26	1		T5	1
valid_sources[0x1d]	26023	1			T5	3		T41	1		T10	1
valid_sources[0x1e]	24790	1			T1	3		T2	1		T30	4
valid_sources[0x1f]	25726	1			T30	2		T37	1		T33	1
valid_sources[0x20]	24961	1			T5	1		T41	1		T10	4
valid_sources[0x21]	25492	1			T5	2		T30	1		T37	1
valid_sources[0x22]	25169	1			T9	7		T37	1		T41	7
valid_sources[0x23]	24977	1			T2	1		T41	1		T10	1
valid_sources[0x24]	24914	1			T2	1		T5	1		T33	1
valid_sources[0x25]	24832	1			T26	1		T37	1		T33	1
valid_sources[0x26]	25117	1			T5	2		T9	36		T30	6
valid_sources[0x27]	25798	1			T5	3		T40	1		T30	1
valid_sources[0x28]	25520	1			T5	3		T31	52		T30	1
valid_sources[0x29]	25877	1			T37	2		T32	1		T41	4
valid_sources[0x2a]	25857	1			T36	1		T5	1		T41	10
valid_sources[0x2b]	25454	1			T1	1		T30	4		T37	2
valid_sources[0x2c]	25985	1			T30	4		T41	1		T10	2
valid_sources[0x2d]	26274	1			T26	1		T37	1		T41	3
valid_sources[0x2e]	24622	1			T26	1		T37	2		T41	1
valid_sources[0x2f]	25078	1			T2	1		T36	1		T37	1
valid_sources[0x30]	25078	1			T2	1		T41	3		T10	1
valid_sources[0x31]	25878	1			T2	1		T5	1		T33	1
valid_sources[0x32]	24470	1			T26	1		T5	2		T37	1
valid_sources[0x33]	25354	1			T2	1		T5	1		T32	2
valid_sources[0x34]	26071	1			T5	1		T37	1		T32	2
valid_sources[0x35]	26220	1			T32	1		T10	1		T27	642
valid_sources[0x36]	23223	1			T5	2		T33	2		T41	3
valid_sources[0x37]	23730	1			T5	3		T30	1		T41	1
valid_sources[0x38]	24783	1			T26	1		T5	1		T30	4
valid_sources[0x39]	25038	1			T4	31		T5	1		T37	1
valid_sources[0x3a]	25277	1			T5	1		T9	7		T37	1
valid_sources[0x3b]	25715	1			T2	2		T36	1		T5	2
valid_sources[0x3c]	25759	1			T2	1		T5	4		T30	5
valid_sources[0x3d]	26574	1			T5	1		T33	1		T10	2
valid_sources[0x3e]	26060	1			T5	3		T37	1		T32	1
valid_sources[0x3f]	24262	1			T2	1		T5	1		T30	2
valid_sources[0x40]	25636	1			T5	2		T37	1		T33	2
valid_sources[0x41]	24685	1			T5	1		T37	1		T32	1
valid_sources[0x42]	24711	1			T37	1		T10	3		T27	634
valid_sources[0x43]	26334	1			T2	1		T30	1		T37	2
valid_sources[0x44]	24541	1			T26	1		T10	2		T27	649
valid_sources[0x45]	26451	1			T30	8		T32	2		T41	2
valid_sources[0x46]	24797	1			T2	1		T5	1		T37	1
valid_sources[0x47]	25145	1			T5	3		T37	1		T41	5
valid_sources[0x48]	25363	1			T5	2		T37	1		T41	1
valid_sources[0x49]	24733	1			T1	3		T2	1		T36	1
valid_sources[0x4a]	25107	1			T1	1		T5	1		T40	1
valid_sources[0x4b]	24480	1			T37	2		T41	4		T10	1
valid_sources[0x4c]	27462	1			T2	1		T37	1		T27	673
valid_sources[0x4d]	25090	1			T5	4		T9	2		T37	2
valid_sources[0x4e]	25048	1			T5	2		T23	2		T37	1
valid_sources[0x4f]	26335	1			T5	3		T30	2		T37	1
valid_sources[0x50]	25276	1			T5	2		T41	2		T27	651
valid_sources[0x51]	25043	1			T2	1		T41	2		T10	1
valid_sources[0x52]	25405	1			T5	5		T41	3		T27	695
valid_sources[0x53]	26155	1			T2	3		T5	4		T27	634
valid_sources[0x54]	26163	1			T2	2		T5	2		T35	4
valid_sources[0x55]	24993	1			T2	2		T23	3		T41	2
valid_sources[0x56]	24406	1			T2	1		T5	5		T10	1
valid_sources[0x57]	24851	1			T5	5		T30	1		T10	1
valid_sources[0x58]	26769	1			T9	1		T41	5		T10	4
valid_sources[0x59]	25436	1			T5	2		T37	1		T41	4
valid_sources[0x5a]	25370	1			T2	1		T36	10		T5	3
valid_sources[0x5b]	26058	1			T1	7		T5	1		T33	2
valid_sources[0x5c]	25906	1			T2	1		T5	3		T37	1
valid_sources[0x5d]	25381	1			T2	2		T36	1		T5	2
valid_sources[0x5e]	24478	1			T5	2		T40	2		T37	1
valid_sources[0x5f]	25866	1			T41	1		T10	1		T27	646
valid_sources[0x60]	24785	1			T2	3		T5	4		T30	1
valid_sources[0x61]	24088	1			T5	1		T23	5		T37	1
valid_sources[0x62]	25064	1			T35	3		T27	649		T11	3
valid_sources[0x63]	25999	1			T41	5		T10	1		T27	605
valid_sources[0x64]	25017	1			T5	1		T37	1		T41	4
valid_sources[0x65]	24877	1			T2	1		T5	2		T37	1
valid_sources[0x66]	26095	1			T2	1		T5	1		T41	6
valid_sources[0x67]	24477	1			T2	3		T26	1		T9	7
valid_sources[0x68]	24557	1			T2	1		T26	2		T41	5
valid_sources[0x69]	24724	1			T2	2		T36	14		T5	1
valid_sources[0x6a]	25007	1			T5	4		T40	2		T37	1
valid_sources[0x6b]	24364	1			T2	1		T26	1		T5	1
valid_sources[0x6c]	24063	1			T5	1		T40	1		T37	1
valid_sources[0x6d]	26104	1			T2	1		T41	4		T10	1
valid_sources[0x6e]	26380	1			T2	3		T26	1		T5	4
valid_sources[0x6f]	25195	1			T41	2		T35	1		T27	739
valid_sources[0x70]	24806	1			T37	1		T33	1		T41	1
valid_sources[0x71]	24714	1			T5	1		T30	2		T37	2
valid_sources[0x72]	23791	1			T5	1		T33	1		T41	1
valid_sources[0x73]	24501	1			T40	1		T30	1		T37	1
valid_sources[0x74]	24735	1			T2	1		T5	7		T30	1
valid_sources[0x75]	25804	1			T2	1		T26	1		T5	2
valid_sources[0x76]	25048	1			T5	1		T30	1		T37	1
valid_sources[0x77]	25077	1			T2	1		T5	1		T37	1
valid_sources[0x78]	25703	1			T31	14		T10	1		T27	707
valid_sources[0x79]	26606	1			T37	1		T41	1		T27	660
valid_sources[0x7a]	27171	1			T35	2		T27	618		T11	1
valid_sources[0x7b]	25549	1			T2	2		T5	1		T24	120
valid_sources[0x7c]	24614	1			T5	1		T10	1		T27	690
valid_sources[0x7d]	24589	1			T2	1		T5	3		T41	6
valid_sources[0x7e]	24422	1			T37	1		T33	1		T41	6
valid_sources[0x7f]	25951	1			T2	1		T37	1		T33	1
valid_sources[0x80]	24174	1			T2	1		T5	2		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1456687

1

T1

5

T2

5

T3

3

values[0x0]

all_enables

biggest_size

2161779

1

T1

11

T2

11

T3

2

values[0x1]

all_enables

biggest_size

2156904

1

T1

13

T2

7

T3

3