Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2639	1			T1	2		T2	1		T36	2
non_zero_bins[1]	1965	1			T1	1		T5	2		T25	1
zero	8480	1			T1	1		T4	2		T26	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	518	1			T36	1		T5	2		T41	1
uni	3624	1			T1	1		T26	1		T36	2
gen	3976	1			T1	1		T4	1		T26	1
res	843	1			T1	1		T5	1		T9	2
ins	4123	1			T1	1		T2	1		T4	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8759

1

T1

1

T4

2

T26

2

mubi_true

4325

1

T1

3

T2

1

T26

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T17

1

T18

1

T19

1

pass

13034

1

T1

4

T2

1

T4

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	113	1			T36	1		T5	1		T27	2
upd	non_zero_bins[0]	pass	mubi_true	137	1			T5	1		T27	1		T28	2
upd	non_zero_bins[1]	pass	mubi_false	76	1			T27	1		T29	2		T166	1
upd	non_zero_bins[1]	pass	mubi_true	78	1			T28	3		T29	1		T190	4
upd	zero	pass	mubi_false	55	1			T41	1		T27	2		T29	1
upd	zero	pass	mubi_true	59	1			T27	2		T51	1		T190	2
uni	zero	fail	mubi_false	11	1			T19	1		T84	1		T124	1
uni	zero	pass	mubi_false	2628	1			T1	1		T36	2		T5	3
uni	zero	pass	mubi_true	985	1			T26	1		T5	2		T25	1
gen	non_zero_bins[0]	pass	mubi_false	501	1			T9	1		T41	3		T10	2
gen	non_zero_bins[0]	pass	mubi_true	504	1			T1	1		T24	1		T31	1
gen	non_zero_bins[1]	pass	mubi_false	314	1			T9	3		T27	2		T11	12
gen	non_zero_bins[1]	pass	mubi_true	373	1			T5	1		T25	1		T41	1
gen	zero	fail	mubi_false	22	1			T18	1		T105	1		T64	1
gen	zero	pass	mubi_false	1818	1			T4	1		T26	1		T5	3
gen	zero	pass	mubi_true	444	1			T36	2		T5	1		T34	1
res	non_zero_bins[0]	pass	mubi_false	175	1			T41	1		T10	2		T49	1
res	non_zero_bins[0]	pass	mubi_true	185	1			T1	1		T32	1		T27	1
res	non_zero_bins[1]	pass	mubi_false	161	1			T9	2		T41	1		T27	1
res	non_zero_bins[1]	pass	mubi_true	145	1			T5	1		T50	1		T28	1
res	zero	fail	mubi_false	3	1			T66	1		T187	1		T239	1
res	zero	pass	mubi_false	104	1			T27	2		T240	1		T28	2
res	zero	pass	mubi_true	70	1			T41	1		T11	2		T28	2
ins	non_zero_bins[0]	pass	mubi_false	500	1			T5	3		T25	1		T33	1
ins	non_zero_bins[0]	pass	mubi_true	524	1			T2	1		T36	1		T25	1
ins	non_zero_bins[1]	pass	mubi_false	411	1			T9	1		T30	1		T35	1
ins	non_zero_bins[1]	pass	mubi_true	407	1			T1	1		T31	1		T41	1
ins	zero	fail	mubi_false	9	1			T110	1		T241	1		T242	1
ins	zero	fail	mubi_true	5	1			T17	1		T109	1		T243	1
ins	zero	pass	mubi_false	1858	1			T4	1		T26	1		T36	1
ins	zero	pass	mubi_true	409	1			T34	1		T31	1		T30	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded