Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	227609761	10268112	0	0
boot_gen_cmd_rd_A	227609761	52773	0	0
boot_ins_cmd_rd_A	227609761	60775	0	0
ctrl_rd_A	227609761	51941	0	0
err_code_test_rd_A	227609761	60501	0	0
intr_enable_rd_A	227609761	58762	0	0
max_num_reqs_between_reseeds_rd_A	227609761	52627	0	0
regwen_rd_A	227609761	60480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	10268112	0	0
T11	3932	0	0	0
T16	1686	0	0	0
T17	1677	0	0	0
T27	675980	274803	0	0
T28	0	134060	0	0
T29	0	363639	0	0
T38	4674	0	0	0
T54	2183	0	0	0
T55	576	0	0	0
T56	788	0	0	0
T137	1938	0	0	0
T166	0	203443	0	0
T167	0	225233	0	0
T170	1075	0	0	0
T190	0	313980	0	0
T191	0	101514	0	0
T192	0	105374	0	0
T193	0	97533	0	0
T194	0	53522	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	52773	0	0
T98	723	0	0	0
T132	1247	0	0	0
T166	597948	6050	0	0
T167	547351	0	0	0
T193	0	2878	0	0
T195	0	3292	0	0
T196	0	7274	0	0
T197	0	4236	0	0
T198	0	2152	0	0
T199	0	3356	0	0
T200	0	4670	0	0
T201	0	523	0	0
T202	0	1867	0	0
T203	3557	0	0	0
T204	2136	0	0	0
T205	2130	0	0	0
T206	1017	0	0	0
T207	1532	0	0	0
T208	3532	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	60775	0	0
T98	723	0	0	0
T132	1247	0	0	0
T166	597948	6858	0	0
T167	547351	0	0	0
T193	0	3190	0	0
T195	0	3954	0	0
T196	0	8243	0	0
T197	0	4961	0	0
T198	0	2646	0	0
T199	0	3788	0	0
T200	0	5684	0	0
T201	0	658	0	0
T202	0	2126	0	0
T203	3557	0	0	0
T204	2136	0	0	0
T205	2130	0	0	0
T206	1017	0	0	0
T207	1532	0	0	0
T208	3532	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	51941	0	0
T11	3932	0	0	0
T16	1686	0	0	0
T17	1677	0	0	0
T27	675980	0	0	0
T35	4310	6	0	0
T38	4674	0	0	0
T45	0	8	0	0
T54	2183	0	0	0
T56	788	0	0	0
T137	1938	0	0	0
T166	0	5922	0	0
T170	1075	0	0	0
T171	0	7	0	0
T193	0	2739	0	0
T195	0	3337	0	0
T196	0	6644	0	0
T197	0	4242	0	0
T209	0	3	0	0
T210	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	60501	0	0
T98	723	0	0	0
T132	1247	0	0	0
T166	597948	6764	0	0
T167	547351	0	0	0
T193	0	3252	0	0
T195	0	4277	0	0
T196	0	8158	0	0
T197	0	4695	0	0
T198	0	2445	0	0
T199	0	3838	0	0
T200	0	5578	0	0
T201	0	521	0	0
T202	0	2177	0	0
T203	3557	0	0	0
T204	2136	0	0	0
T205	2130	0	0	0
T206	1017	0	0	0
T207	1532	0	0	0
T208	3532	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	58762	0	0
T10	5127	0	0	0
T11	3932	0	0	0
T15	692	0	0	0
T16	1686	0	0	0
T17	1677	0	0	0
T27	675980	0	0	0
T35	4310	0	0	0
T41	15581	46	0	0
T54	2183	0	0	0
T164	1734	0	0	0
T166	0	6398	0	0
T171	0	34	0	0
T193	0	3285	0	0
T195	0	3855	0	0
T196	0	7571	0	0
T209	0	93	0	0
T211	0	16	0	0
T212	0	11	0	0
T213	0	23	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	52627	0	0
T98	723	0	0	0
T132	1247	0	0	0
T166	597948	5830	0	0
T167	547351	0	0	0
T193	0	2743	0	0
T195	0	3405	0	0
T196	0	6830	0	0
T197	0	4148	0	0
T198	0	2353	0	0
T199	0	3329	0	0
T200	0	4755	0	0
T201	0	610	0	0
T202	0	2012	0	0
T203	3557	0	0	0
T204	2136	0	0	0
T205	2130	0	0	0
T206	1017	0	0	0
T207	1532	0	0	0
T208	3532	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227609761	60480	0	0
T98	723	0	0	0
T132	1247	0	0	0
T166	597948	6834	0	0
T167	547351	0	0	0
T193	0	3452	0	0
T195	0	3799	0	0
T196	0	8474	0	0
T197	0	4865	0	0
T198	0	2395	0	0
T199	0	3437	0	0
T200	0	5648	0	0
T201	0	587	0	0
T202	0	2163	0	0
T203	3557	0	0	0
T204	2136	0	0	0
T205	2130	0	0	0
T206	1017	0	0	0
T207	1532	0	0	0
T208	3532	0	0	0