Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	669834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5546468

1

T1

6

T2

86554

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1635936	1			T1	52		T2	27533		T3	46
values[0x0]	2119069	1			T1	4		T2	32997		T3	10
values[0x1]	2461297	1			T1	3		T2	38812		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	327864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5888438

1

T1

27

T2

92788

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22899	1			T2	269		T4	585		T5	605
valid_sources[0x01]	25490	1			T2	225		T12	1		T4	728
valid_sources[0x02]	23547	1			T2	111		T4	659		T5	945
valid_sources[0x03]	24734	1			T2	699		T4	668		T5	817
valid_sources[0x04]	25397	1			T2	350		T4	656		T5	690
valid_sources[0x05]	25206	1			T2	662		T4	659		T5	744
valid_sources[0x06]	24405	1			T2	443		T4	712		T5	783
valid_sources[0x07]	25169	1			T2	497		T4	635		T5	1180
valid_sources[0x08]	23007	1			T2	46		T4	700		T5	1451
valid_sources[0x09]	22345	1			T2	31		T12	3		T9	1
valid_sources[0x0a]	26088	1			T2	636		T12	3		T4	639
valid_sources[0x0b]	26638	1			T2	300		T12	1		T4	650
valid_sources[0x0c]	25062	1			T2	338		T12	1		T9	1
valid_sources[0x0d]	23662	1			T2	828		T4	679		T5	357
valid_sources[0x0e]	24304	1			T2	388		T12	2		T4	692
valid_sources[0x0f]	21762	1			T2	260		T4	709		T5	1017
valid_sources[0x10]	25618	1			T2	406		T12	1		T4	715
valid_sources[0x11]	24124	1			T2	81		T12	2		T4	698
valid_sources[0x12]	23405	1			T2	464		T4	687		T5	680
valid_sources[0x13]	24599	1			T2	637		T4	642		T5	1036
valid_sources[0x14]	24162	1			T2	271		T12	1		T4	649
valid_sources[0x15]	23891	1			T2	578		T12	3		T9	1
valid_sources[0x16]	26070	1			T2	439		T9	1		T4	672
valid_sources[0x17]	24450	1			T2	72		T12	4		T9	2
valid_sources[0x18]	23722	1			T2	348		T4	642		T5	1244
valid_sources[0x19]	24413	1			T2	634		T12	3		T4	703
valid_sources[0x1a]	22771	1			T2	374		T12	1		T4	653
valid_sources[0x1b]	24014	1			T2	645		T12	2		T9	1
valid_sources[0x1c]	23456	1			T2	200		T12	3		T4	670
valid_sources[0x1d]	23459	1			T2	368		T4	696		T5	1021
valid_sources[0x1e]	23295	1			T2	252		T4	671		T5	580
valid_sources[0x1f]	22372	1			T2	190		T12	2		T4	658
valid_sources[0x20]	26220	1			T2	572		T4	687		T5	422
valid_sources[0x21]	23704	1			T2	346		T4	713		T5	761
valid_sources[0x22]	25370	1			T2	917		T9	1		T4	584
valid_sources[0x23]	23306	1			T2	439		T12	2		T4	597
valid_sources[0x24]	25163	1			T2	169		T4	678		T5	1548
valid_sources[0x25]	23339	1			T2	548		T12	3		T4	673
valid_sources[0x26]	23122	1			T2	536		T9	1		T4	621
valid_sources[0x27]	24649	1			T2	107		T12	2		T9	1
valid_sources[0x28]	25087	1			T2	524		T12	4		T9	2
valid_sources[0x29]	25096	1			T2	306		T4	699		T5	1038
valid_sources[0x2a]	25974	1			T2	1086		T12	2		T9	2
valid_sources[0x2b]	26473	1			T2	633		T12	4		T9	1
valid_sources[0x2c]	22362	1			T2	683		T12	1		T4	620
valid_sources[0x2d]	24599	1			T2	539		T12	4		T4	607
valid_sources[0x2e]	26537	1			T1	59		T2	300		T12	1
valid_sources[0x2f]	24742	1			T2	422		T12	2		T4	686
valid_sources[0x30]	23225	1			T2	358		T9	1		T4	697
valid_sources[0x31]	25688	1			T2	112		T12	1		T4	700
valid_sources[0x32]	24241	1			T2	121		T4	666		T5	1188
valid_sources[0x33]	23910	1			T2	108		T12	1		T9	1
valid_sources[0x34]	23996	1			T2	153		T4	645		T5	765
valid_sources[0x35]	24875	1			T2	57		T4	649		T5	815
valid_sources[0x36]	24715	1			T2	845		T12	2		T4	672
valid_sources[0x37]	23954	1			T2	101		T12	2		T9	1
valid_sources[0x38]	24843	1			T2	208		T12	4		T4	623
valid_sources[0x39]	23089	1			T2	208		T9	1		T4	685
valid_sources[0x3a]	22995	1			T2	106		T4	675		T5	96
valid_sources[0x3b]	23933	1			T2	789		T12	1		T9	1
valid_sources[0x3c]	25201	1			T2	109		T4	673		T5	1622
valid_sources[0x3d]	22026	1			T2	447		T12	1		T4	681
valid_sources[0x3e]	26266	1			T2	337		T9	1		T4	684
valid_sources[0x3f]	24034	1			T2	658		T4	654		T5	540
valid_sources[0x40]	23691	1			T2	372		T12	1		T4	612
valid_sources[0x41]	23541	1			T2	485		T4	708		T5	708
valid_sources[0x42]	23618	1			T2	503		T12	4		T4	672
valid_sources[0x43]	22206	1			T2	327		T4	694		T5	749
valid_sources[0x44]	21258	1			T2	24		T4	673		T5	328
valid_sources[0x45]	23111	1			T2	510		T12	1		T4	650
valid_sources[0x46]	25631	1			T2	908		T9	2		T4	713
valid_sources[0x47]	25596	1			T2	309		T12	1		T9	1
valid_sources[0x48]	24484	1			T2	291		T9	1		T4	632
valid_sources[0x49]	23026	1			T2	245		T4	637		T5	59
valid_sources[0x4a]	24289	1			T2	47		T12	4		T4	586
valid_sources[0x4b]	24309	1			T2	459		T12	1		T4	654
valid_sources[0x4c]	22953	1			T2	99		T4	588		T5	1473
valid_sources[0x4d]	23604	1			T2	594		T12	2		T4	658
valid_sources[0x4e]	23631	1			T2	541		T4	653		T5	1001
valid_sources[0x4f]	23562	1			T2	426		T4	645		T5	995
valid_sources[0x50]	23422	1			T2	187		T12	3		T9	1
valid_sources[0x51]	26433	1			T2	959		T12	2		T4	665
valid_sources[0x52]	25141	1			T2	633		T12	1		T9	1
valid_sources[0x53]	25058	1			T2	425		T9	1		T4	712
valid_sources[0x54]	24221	1			T2	259		T4	675		T5	1118
valid_sources[0x55]	23367	1			T2	340		T4	716		T5	865
valid_sources[0x56]	24685	1			T2	918		T4	631		T5	360
valid_sources[0x57]	23577	1			T2	160		T9	1		T4	610
valid_sources[0x58]	22150	1			T2	70		T12	1		T4	678
valid_sources[0x59]	23848	1			T2	467		T4	651		T5	996
valid_sources[0x5a]	25386	1			T2	198		T4	660		T5	2108
valid_sources[0x5b]	22376	1			T2	137		T4	626		T5	1140
valid_sources[0x5c]	24493	1			T2	434		T12	1		T4	663
valid_sources[0x5d]	26003	1			T2	181		T4	629		T5	1741
valid_sources[0x5e]	23061	1			T2	251		T12	2		T4	619
valid_sources[0x5f]	23330	1			T2	661		T12	1		T9	1
valid_sources[0x60]	26182	1			T2	413		T12	1		T4	672
valid_sources[0x61]	22833	1			T2	26		T12	2		T9	2
valid_sources[0x62]	25663	1			T2	617		T12	2		T4	744
valid_sources[0x63]	23592	1			T2	32		T4	671		T5	1265
valid_sources[0x64]	24439	1			T2	162		T12	4		T4	667
valid_sources[0x65]	24015	1			T2	484		T9	1		T4	696
valid_sources[0x66]	26566	1			T2	459		T4	669		T5	415
valid_sources[0x67]	24582	1			T2	277		T12	1		T4	644
valid_sources[0x68]	22140	1			T2	156		T4	648		T5	318
valid_sources[0x69]	24051	1			T2	319		T12	2		T4	662
valid_sources[0x6a]	25695	1			T2	1068		T12	1		T4	625
valid_sources[0x6b]	22546	1			T2	562		T4	719		T5	987
valid_sources[0x6c]	23349	1			T2	407		T9	2		T4	738
valid_sources[0x6d]	26548	1			T2	512		T12	1		T9	2
valid_sources[0x6e]	23640	1			T2	515		T12	2		T4	611
valid_sources[0x6f]	24743	1			T2	28		T12	1		T4	654
valid_sources[0x70]	25634	1			T2	570		T4	621		T5	541
valid_sources[0x71]	24199	1			T2	618		T12	3		T9	1
valid_sources[0x72]	23420	1			T2	38		T12	2		T4	726
valid_sources[0x73]	25129	1			T2	437		T4	601		T5	892
valid_sources[0x74]	22856	1			T2	529		T4	651		T5	1092
valid_sources[0x75]	27993	1			T2	553		T9	1		T4	716
valid_sources[0x76]	24829	1			T2	167		T12	1		T9	1
valid_sources[0x77]	24472	1			T2	160		T12	2		T9	1
valid_sources[0x78]	23994	1			T2	144		T4	682		T5	401
valid_sources[0x79]	22977	1			T2	660		T12	1		T4	675
valid_sources[0x7a]	24783	1			T2	747		T12	1		T4	708
valid_sources[0x7b]	23327	1			T2	676		T12	2		T4	656
valid_sources[0x7c]	21881	1			T2	340		T9	1		T4	659
valid_sources[0x7d]	23977	1			T2	678		T9	1		T4	608
valid_sources[0x7e]	26072	1			T2	734		T12	1		T9	1
valid_sources[0x7f]	22908	1			T2	291		T12	1		T4	686
valid_sources[0x80]	23002	1			T2	880		T12	1		T4	646

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1397788

1

T1

3

T2

21686

T3

5

values[0x0]

all_enables

biggest_size

2076940

1

T1

1

T2

32337

T3

9

values[0x1]

all_enables

biggest_size

2071740

1

T1

2

T2

32531

T3

18