Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2648	1			T2	68		T3	2		T12	2
non_zero_bins[1]	1731	1			T2	37		T3	1		T12	7
zero	8455	1			T1	3		T2	171		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	473	1			T2	13		T3	1		T4	12
uni	3593	1			T1	1		T2	86		T3	2
gen	3885	1			T1	1		T2	72		T3	2
res	800	1			T2	17		T12	2		T9	4
ins	4083	1			T1	1		T2	88		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8792

1

T1

2

T2

180

T3

5

mubi_true

4042

1

T1

1

T2

96

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T18

1

T19

1

T20

1

pass

12784

1

T1

3

T2

276

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	118	1			T2	3		T4	2		T5	1
upd	non_zero_bins[0]	pass	mubi_true	108	1			T2	4		T4	3		T5	3
upd	non_zero_bins[1]	pass	mubi_false	75	1			T2	2		T3	1		T4	1
upd	non_zero_bins[1]	pass	mubi_true	69	1			T2	2		T5	5		T132	1
upd	zero	pass	mubi_false	55	1			T2	1		T4	3		T150	2
upd	zero	pass	mubi_true	48	1			T2	1		T4	3		T132	1
uni	zero	fail	mubi_false	12	1			T18	1		T20	1		T130	1
uni	zero	pass	mubi_false	2630	1			T2	67		T3	2		T12	1
uni	zero	pass	mubi_true	951	1			T1	1		T2	19		T4	16
gen	non_zero_bins[0]	pass	mubi_false	480	1			T2	10		T4	7		T5	4
gen	non_zero_bins[0]	pass	mubi_true	480	1			T2	10		T3	1		T9	2
gen	non_zero_bins[1]	pass	mubi_false	312	1			T2	5		T12	5		T4	4
gen	non_zero_bins[1]	pass	mubi_true	305	1			T2	7		T12	1		T4	5
gen	zero	fail	mubi_false	23	1			T19	1		T54	1		T104	1
gen	zero	pass	mubi_false	1880	1			T1	1		T2	31		T3	1
gen	zero	pass	mubi_true	405	1			T2	9		T4	3		T5	3
res	non_zero_bins[0]	pass	mubi_false	197	1			T2	6		T4	2		T10	2
res	non_zero_bins[0]	pass	mubi_true	185	1			T2	4		T12	2		T9	4
res	non_zero_bins[1]	pass	mubi_false	139	1			T2	2		T4	1		T5	1
res	non_zero_bins[1]	pass	mubi_true	116	1			T2	1		T4	1		T33	1
res	zero	fail	mubi_false	9	1			T71	1		T72	1		T177	1
res	zero	pass	mubi_false	63	1			T2	1		T5	1		T132	1
res	zero	pass	mubi_true	91	1			T2	3		T4	1		T132	1
ins	non_zero_bins[0]	pass	mubi_false	524	1			T2	9		T3	1		T4	5
ins	non_zero_bins[0]	pass	mubi_true	556	1			T2	22		T9	1		T4	4
ins	non_zero_bins[1]	pass	mubi_false	385	1			T2	9		T12	1		T4	7
ins	non_zero_bins[1]	pass	mubi_true	330	1			T2	9		T4	11		T10	1
ins	zero	fail	mubi_false	5	1			T110	1		T111	1		T112	1
ins	zero	fail	mubi_true	1	1			T248	1		-	-		-	-
ins	zero	pass	mubi_false	1885	1			T1	1		T2	34		T4	34
ins	zero	pass	mubi_true	397	1			T2	5		T3	1		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded