Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218193304	9776481	0	0
boot_gen_cmd_rd_A	218193304	68589	0	0
boot_ins_cmd_rd_A	218193304	77374	0	0
ctrl_rd_A	218193304	69012	0	0
err_code_test_rd_A	218193304	78218	0	0
intr_enable_rd_A	218193304	77004	0	0
max_num_reqs_between_reseeds_rd_A	218193304	67841	0	0
regwen_rd_A	218193304	78480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	9776481	0	0
T2	278464	157265	0	0
T3	3913	0	0	0
T4	509739	278747	0	0
T5	928933	377464	0	0
T9	2812	0	0	0
T10	4301	0	0	0
T12	2989	0	0	0
T25	779	0	0	0
T41	1174	0	0	0
T55	0	67119	0	0
T61	0	268929	0	0
T132	558836	315514	0	0
T150	0	118853	0	0
T187	0	334160	0	0
T188	0	75959	0	0
T189	0	114674	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	68589	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	3641	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1279	0	0
T191	0	1898	0	0
T192	0	7544	0	0
T193	0	942	0	0
T194	0	651	0	0
T195	0	2605	0	0
T196	0	8195	0	0
T197	0	1919	0	0
T198	0	6776	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	77374	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	3773	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1510	0	0
T191	0	2070	0	0
T192	0	8859	0	0
T193	0	964	0	0
T194	0	884	0	0
T195	0	3172	0	0
T196	0	9454	0	0
T197	0	2151	0	0
T198	0	7550	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	69012	0	0
T6	782	0	0	0
T15	1377	0	0	0
T24	1384	0	0	0
T26	2621	0	0	0
T27	848	0	0	0
T32	2432	0	0	0
T43	1190	0	0	0
T50	2963	0	0	0
T51	4581	0	0	0
T63	0	3	0	0
T133	1484	4	0	0
T150	0	3775	0	0
T190	0	1154	0	0
T191	0	1828	0	0
T192	0	8038	0	0
T193	0	1091	0	0
T203	0	6	0	0
T204	0	1	0	0
T205	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	78218	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	4203	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1286	0	0
T191	0	2373	0	0
T192	0	8510	0	0
T193	0	1099	0	0
T194	0	743	0	0
T195	0	3310	0	0
T196	0	9353	0	0
T197	0	2278	0	0
T198	0	7666	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	77004	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	4214	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1481	0	0
T191	0	2195	0	0
T192	0	8042	0	0
T193	0	1300	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0
T206	0	77	0	0
T207	0	41	0	0
T208	0	3	0	0
T209	0	52	0	0
T210	0	28	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	67841	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	3294	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1192	0	0
T191	0	1889	0	0
T192	0	7488	0	0
T193	0	1134	0	0
T194	0	590	0	0
T195	0	2782	0	0
T196	0	8481	0	0
T197	0	1808	0	0
T198	0	6843	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218193304	78480	0	0
T14	2161	0	0	0
T17	1819	0	0	0
T131	1111	0	0	0
T150	342493	4027	0	0
T178	2813	0	0	0
T180	6213	0	0	0
T190	0	1342	0	0
T191	0	2048	0	0
T192	0	8634	0	0
T193	0	1124	0	0
T194	0	804	0	0
T195	0	2869	0	0
T196	0	9464	0	0
T197	0	2333	0	0
T198	0	7867	0	0
T199	1206	0	0	0
T200	3856	0	0	0
T201	948	0	0	0
T202	1445	0	0	0