Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2597	1			T2	3		T21	1		T33	1
non_zero_bins[1]	1840	1			T2	2		T41	1		T23	15
zero	8304	1			T1	2		T3	3		T21	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	511	1			T41	1		T23	5		T24	10
uni	3522	1			T3	1		T21	2		T22	1
gen	3845	1			T1	1		T2	2		T3	1
res	829	1			T2	2		T21	1		T23	8
ins	4034	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8689

1

T1

2

T2

3

T3

3

mubi_true

4052

1

T2

2

T21

1

T22

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T16

1

T17

1

T12

1

pass

12691

1

T1

2

T2

5

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	107	1			T150	1		T155	2		T216	1
upd	non_zero_bins[0]	pass	mubi_true	120	1			T23	2		T24	5		T155	1
upd	non_zero_bins[1]	pass	mubi_false	100	1			T41	1		T23	1		T24	2
upd	non_zero_bins[1]	pass	mubi_true	78	1			T23	1		T24	2		T155	1
upd	zero	pass	mubi_false	46	1			T24	1		T34	1		T148	1
upd	zero	pass	mubi_true	60	1			T23	1		T30	1		T25	1
uni	zero	fail	mubi_false	12	1			T127	1		T128	1		T129	1
uni	zero	pass	mubi_false	2587	1			T3	1		T21	2		T33	1
uni	zero	pass	mubi_true	923	1			T22	1		T23	4		T40	1
gen	non_zero_bins[0]	pass	mubi_false	473	1			T21	1		T23	5		T24	5
gen	non_zero_bins[0]	pass	mubi_true	456	1			T41	1		T23	4		T24	7
gen	non_zero_bins[1]	pass	mubi_false	340	1			T2	2		T23	3		T24	5
gen	non_zero_bins[1]	pass	mubi_true	326	1			T23	1		T40	1		T71	1
gen	zero	fail	mubi_false	29	1			T17	1		T12	1		T77	1
gen	zero	pass	mubi_false	1820	1			T1	1		T3	1		T21	1
gen	zero	pass	mubi_true	401	1			T27	2		T16	2		T24	5
res	non_zero_bins[0]	pass	mubi_false	198	1			T23	2		T40	1		T24	2
res	non_zero_bins[0]	pass	mubi_true	186	1			T2	2		T23	2		T9	2
res	non_zero_bins[1]	pass	mubi_false	142	1			T23	2		T24	2		T8	2
res	non_zero_bins[1]	pass	mubi_true	130	1			T23	1		T24	1		T151	1
res	zero	fail	mubi_false	4	1			T256	1		T257	1		T199	1
res	zero	pass	mubi_false	85	1			T24	2		T75	4		T25	1
res	zero	pass	mubi_true	84	1			T21	1		T23	1		T24	2
ins	non_zero_bins[0]	pass	mubi_false	527	1			T2	1		T33	1		T41	1
ins	non_zero_bins[0]	pass	mubi_true	530	1			T23	4		T24	9		T153	2
ins	non_zero_bins[1]	pass	mubi_false	332	1			T23	2		T24	2		T8	1
ins	non_zero_bins[1]	pass	mubi_true	392	1			T23	4		T26	1		T40	1
ins	zero	fail	mubi_false	5	1			T16	1		T114	1		T115	1
ins	zero	pass	mubi_false	1882	1			T1	1		T3	1		T21	2
ins	zero	pass	mubi_true	366	1			T33	1		T27	2		T31	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded