Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215277025	9310286	0	0
boot_gen_cmd_rd_A	215277025	86047	0	0
boot_ins_cmd_rd_A	215277025	98210	0	0
ctrl_rd_A	215277025	85888	0	0
err_code_test_rd_A	215277025	99544	0	0
intr_enable_rd_A	215277025	94608	0	0
max_num_reqs_between_reseeds_rd_A	215277025	85992	0	0
regwen_rd_A	215277025	99269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	9310286	0	0
T8	5260	0	0	0
T16	1978	0	0	0
T23	219301	126344	0	0
T24	308801	178103	0	0
T25	0	194449	0	0
T26	3028	0	0	0
T40	8331	0	0	0
T65	815	0	0	0
T148	0	118525	0	0
T149	0	117470	0	0
T150	18065	0	0	0
T153	7335	0	0	0
T165	1104	0	0	0
T204	0	282641	0	0
T205	0	119595	0	0
T206	0	203397	0	0
T207	0	161701	0	0
T208	0	417624	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	86047	0	0
T25	576047	5679	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T94	2713	0	0	0
T149	0	3557	0	0
T154	3267	0	0	0
T206	0	3328	0	0
T209	0	3852	0	0
T210	0	4308	0	0
T211	0	1368	0	0
T212	0	3683	0	0
T213	0	2188	0	0
T214	0	2294	0	0
T215	0	2805	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	98210	0	0
T25	576047	6589	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T94	2713	0	0	0
T149	0	3932	0	0
T154	3267	0	0	0
T206	0	3554	0	0
T209	0	4855	0	0
T210	0	5422	0	0
T211	0	1494	0	0
T212	0	4730	0	0
T213	0	2641	0	0
T214	0	2632	0	0
T215	0	2889	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	85888	0	0
T25	576047	5638	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T45	0	6	0	0
T46	0	3	0	0
T94	2713	0	0	0
T149	0	3406	0	0
T154	3267	0	0	0
T206	0	3029	0	0
T209	0	3709	0	0
T210	0	4304	0	0
T211	0	1550	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0
T220	0	5	0	0
T221	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	99544	0	0
T25	576047	6665	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T94	2713	0	0	0
T149	0	3875	0	0
T154	3267	0	0	0
T206	0	3652	0	0
T209	0	4673	0	0
T210	0	5212	0	0
T211	0	1733	0	0
T212	0	4628	0	0
T213	0	2648	0	0
T214	0	2314	0	0
T215	0	3196	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	94608	0	0
T12	2044	0	0	0
T17	1943	0	0	0
T25	0	6276	0	0
T65	815	0	0	0
T70	1292	0	0	0
T149	0	3807	0	0
T150	18065	60	0	0
T151	2287	0	0	0
T152	925	0	0	0
T153	7335	5	0	0
T206	0	3465	0	0
T209	0	4459	0	0
T210	0	4925	0	0
T211	0	1899	0	0
T220	0	8	0	0
T222	0	17	0	0
T223	2380	0	0	0
T224	1090	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	85992	0	0
T25	576047	5498	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T94	2713	0	0	0
T149	0	3384	0	0
T154	3267	0	0	0
T206	0	2988	0	0
T209	0	3531	0	0
T210	0	4228	0	0
T211	0	1628	0	0
T212	0	3596	0	0
T213	0	2109	0	0
T214	0	2274	0	0
T215	0	2451	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215277025	99269	0	0
T25	576047	6264	0	0
T34	2923	0	0	0
T35	2341	0	0	0
T36	3868	0	0	0
T94	2713	0	0	0
T149	0	4083	0	0
T154	3267	0	0	0
T206	0	3705	0	0
T209	0	4432	0	0
T210	0	5075	0	0
T211	0	1696	0	0
T212	0	4339	0	0
T213	0	2482	0	0
T214	0	2475	0	0
T215	0	3040	0	0
T216	2012	0	0	0
T217	1440	0	0	0
T218	1235	0	0	0
T219	985	0	0	0