Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T166,T167,T168
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T76,T117,T48
DataWait->Error 99 Covered T65,T67,T14
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T2,T3,T21
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T1,T5,T65
default - - - - Covered T6,T68,T7


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 1503381509 974993 0 0
FpvSecCmErrorStEscalate_A 1503381509 981580 0 0
u_state_regs_A 1503350116 1502245019 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1503381509 974993 0 0
T1 14945 7756 0 0
T2 44891 0 0 0
T3 6811 0 0 0
T4 9457 0 0 0
T5 0 4725 0 0
T6 0 2120 0 0
T7 0 4465 0 0
T13 0 7959 0 0
T21 15638 0 0 0
T22 12404 0 0 0
T27 8001 0 0 0
T31 6804 0 0 0
T33 21525 0 0 0
T41 13454 0 0 0
T65 0 3220 0 0
T67 0 7490 0 0
T68 0 7706 0 0
T69 0 1624 0 0
T79 0 7958 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1503381509 981580 0 0
T1 14945 7763 0 0
T2 44891 0 0 0
T3 6811 0 0 0
T4 9457 0 0 0
T5 0 4732 0 0
T6 0 2127 0 0
T7 0 4472 0 0
T13 0 7966 0 0
T21 15638 0 0 0
T22 12404 0 0 0
T27 8001 0 0 0
T31 6804 0 0 0
T33 21525 0 0 0
T41 13454 0 0 0
T65 0 3227 0 0
T67 0 7497 0 0
T68 0 7713 0 0
T69 0 1631 0 0
T79 0 7965 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1503350116 1502245019 0 0
T1 14833 13636 0 0
T2 44891 44219 0 0
T3 6811 6419 0 0
T4 9443 8232 0 0
T21 15638 15036 0 0
T22 12404 11837 0 0
T27 8001 7602 0 0
T31 6804 6328 0 0
T33 21525 21147 0 0
T41 13454 12824 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T2,T26,T16
DataWait 75 Covered T2,T26,T16
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T26,T16
DataWait->AckPls 80 Covered T2,T26,T16
DataWait->Disabled 107 Covered T109,T170,T171
DataWait->Error 99 Covered T103,T172,T104
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T26,T16
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T26,T16
Idle - 1 0 - Covered T2,T26,T16
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T26,T16
DataWait - - - 0 Covered T2,T26,T16
AckPls - - - - Covered T2,T26,T16
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T173
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T174,T175
DataWait->Error 99 Covered T65,T67,T15
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T176
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T69



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T2,T3,T21
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T1,T5,T65
default - - - - Covered T6,T68,T7


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 137099 0 0
FpvSecCmErrorStEscalate_A 214768787 138040 0 0
u_state_regs_A 214737394 214579523 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 137099 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 260 0 0
T7 0 595 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1058 0 0
T69 0 232 0 0
T79 0 1094 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 138040 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 261 0 0
T7 0 596 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1059 0 0
T69 0 233 0 0
T79 0 1095 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214737394 214579523 0 0
T1 2023 1852 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1337 1164 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T2,T4,T27
DataWait 75 Covered T2,T4,T27
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T166,T168
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T4,T27
DataWait->AckPls 80 Covered T2,T4,T27
DataWait->Disabled 107 Covered T117,T118,T98
DataWait->Error 99 Covered T14,T87,T96
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T4,T27
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T4,T27
Idle - 1 0 - Covered T2,T4,T27
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T4,T27
DataWait - - - 0 Covered T2,T27,T26
AckPls - - - - Covered T2,T4,T27
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T2,T28,T29
DataWait 75 Covered T2,T28,T29
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T177,T178
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T28,T29
DataWait->AckPls 80 Covered T2,T28,T29
DataWait->Disabled 107 Covered T76,T179,T82
DataWait->Error 99 Covered T54,T180,T107
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T28,T29
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T28,T29
Idle - 1 0 - Covered T2,T28,T29
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T28,T29
DataWait - - - 0 Covered T2,T28,T29
AckPls - - - - Covered T2,T28,T29
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T2,T29,T30
DataWait 75 Covered T2,T29,T30
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T167
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T29,T30
DataWait->AckPls 80 Covered T2,T29,T30
DataWait->Disabled 107 Covered T48,T81,T181
DataWait->Error 99 Covered T43,T182,T183
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T29,T30
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T29,T30
Idle - 1 0 - Covered T2,T29,T30
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T29,T30
DataWait - - - 0 Covered T2,T29,T30
AckPls - - - - Covered T2,T29,T30
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T2,T26,T29
DataWait 75 Covered T2,T26,T29
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T184
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T26,T29
DataWait->AckPls 80 Covered T2,T26,T29
DataWait->Disabled 107 Covered T185,T186
DataWait->Error 99 Covered T13,T187,T188
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T26,T29
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T26,T29
Idle - 1 0 - Covered T2,T26,T29
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T26,T29
DataWait - - - 0 Covered T2,T26,T29
AckPls - - - - Covered T2,T26,T29
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T27,T31

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T31,T32,T29
DataWait 75 Covered T31,T32,T29
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T1,T5,T65
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T189
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T31,T32,T29
DataWait->AckPls 80 Covered T31,T32,T29
DataWait->Disabled 107 Covered T75,T97,T190
DataWait->Error 99 Covered T191,T192,T193
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T18,T19,T20
EndPointClear->Disabled 107 Covered T155,T146,T140
EndPointClear->Error 99 Covered T169,T18,T91
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T31,T32,T29
Idle->Disabled 107 Covered T4,T27,T31
Idle->Error 99 Covered T1,T5,T65



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T31,T32,T29
Idle - 1 0 - Covered T31,T32,T29
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T31,T32,T29
DataWait - - - 0 Covered T31,T32,T29
AckPls - - - - Covered T31,T32,T29
Error - - - - Covered T1,T5,T65
default - - - - Covered T18,T19,T20


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T65
0 1 Covered T4,T27,T31
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 214768787 139649 0 0
FpvSecCmErrorStEscalate_A 214768787 140590 0 0
u_state_regs_A 214768787 214610916 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 139649 0 0
T1 2135 1108 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 675 0 0
T6 0 310 0 0
T7 0 645 0 0
T13 0 1137 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 460 0 0
T67 0 1070 0 0
T68 0 1108 0 0
T69 0 232 0 0
T79 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 140590 0 0
T1 2135 1109 0 0
T2 6413 0 0 0
T3 973 0 0 0
T4 1351 0 0 0
T5 0 676 0 0
T6 0 311 0 0
T7 0 646 0 0
T13 0 1138 0 0
T21 2234 0 0 0
T22 1772 0 0 0
T27 1143 0 0 0
T31 972 0 0 0
T33 3075 0 0 0
T41 1922 0 0 0
T65 0 461 0 0
T67 0 1071 0 0
T68 0 1109 0 0
T69 0 233 0 0
T79 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214768787 214610916 0 0
T1 2135 1964 0 0
T2 6413 6317 0 0
T3 973 917 0 0
T4 1351 1178 0 0
T21 2234 2148 0 0
T22 1772 1691 0 0
T27 1143 1086 0 0
T31 972 904 0 0
T33 3075 3021 0 0
T41 1922 1832 0 0