Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.79			70.79

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr	70.79			70.79

---

Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.79			70.79

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.79			70.79

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	202	143	70.79
Total Bits 0->1	101	73	72.28
Total Bits 1->0	101	70	69.31

Ports	8	7	87.50
Port Bits	202	143	70.79
Port Bits 0->1	101	73	72.28
Port Bits 1->0	101	70	69.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T5,*T6,*T7	Yes	T2,T5,T8	INPUT
set_cnt_i[3:1]	No	No		Yes	T9,T10,T11	INPUT
set_cnt_i[31:4]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T2,T8,T12	Yes	T2,T8,T12	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T2,T5,T8	Yes	T2,T5,T8	OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	T2,T5,T8	Yes	T2,T5,T8	OUTPUT
err_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT

*Tests covering at least one bit in the range