| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1808 | 1 | T2 | 3 | T3 | 1 | T27 | 1 | ||||
| auto[2] | 26032 | 1 | T2 | 12 | T3 | 12 | T4 | 1 | ||||
| auto[3] | 25270 | 1 | T2 | 12 | T3 | 12 | T27 | 31 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 130 | 1 | T28 | 1 | T17 | 2 | T14 | 1 | ||||
| auto[2] | 4568 | 1 | T28 | 4 | T17 | 5 | T15 | 1 | ||||
| auto[3] | 4559 | 1 | T28 | 4 | T17 | 5 | T14 | 31 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 142 | 1 | T28 | 1 | T5 | 1 | T10 | 1 | ||||
| auto[2] | 4966 | 1 | T28 | 25 | T5 | 1 | T10 | 16 | ||||
| auto[3] | 4959 | 1 | T28 | 25 | T5 | 1 | T10 | 16 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 126 | 1 | T28 | 1 | T9 | 1 | T23 | 1 | ||||
| auto[2] | 4703 | 1 | T28 | 20 | T9 | 4 | T23 | 1 | ||||
| auto[3] | 4693 | 1 | T28 | 20 | T9 | 4 | T23 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 110 | 1 | T28 | 1 | T9 | 1 | T29 | 1 | ||||
| auto[2] | 4361 | 1 | T28 | 46 | T9 | 1 | T29 | 4 | ||||
| auto[3] | 4352 | 1 | T28 | 46 | T9 | 1 | T29 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 108 | 1 | T14 | 1 | T29 | 1 | T30 | 1 | ||||
| auto[2] | 5674 | 1 | T14 | 1079 | T29 | 28 | T30 | 4 | ||||
| auto[3] | 5668 | 1 | T14 | 1079 | T29 | 28 | T30 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 107 | 1 | T28 | 1 | T14 | 1 | T30 | 1 | ||||
| auto[2] | 2925 | 1 | T28 | 46 | T14 | 9 | T30 | 55 | ||||
| auto[3] | 2921 | 1 | T28 | 46 | T14 | 9 | T30 | 55 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |