Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	741590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6241612

1

T1

2

T2

134

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1832498	1			T1	1		T2	249		T3	32
values[0x0]	2383061	1			T2	67		T3	8		T4	9
values[0x1]	2767643	1			T1	6		T2	66		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	361007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6622195

1

T1

5

T2

200

T3

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25950	1			T31	3		T24	1108		T10	1
valid_sources[0x01]	26499	1			T28	1		T23	1		T31	5
valid_sources[0x02]	27975	1			T31	2		T24	1124		T142	2
valid_sources[0x03]	27993	1			T28	2		T31	2		T24	1183
valid_sources[0x04]	27379	1			T17	2		T31	2		T24	1178
valid_sources[0x05]	27067	1			T31	1		T24	1143		T18	1
valid_sources[0x06]	28530	1			T24	1144		T16	1		T142	1
valid_sources[0x07]	27110	1			T28	1		T17	1		T31	1
valid_sources[0x08]	27234	1			T28	1		T5	7		T31	3
valid_sources[0x09]	26918	1			T28	1		T31	4		T24	1179
valid_sources[0x0a]	31793	1			T28	1		T31	1		T24	1219
valid_sources[0x0b]	26279	1			T31	3		T24	1150		T142	1
valid_sources[0x0c]	28190	1			T28	1		T31	9		T24	1080
valid_sources[0x0d]	27037	1			T31	5		T24	1123		T142	2
valid_sources[0x0e]	26858	1			T24	1200		T174	1		T142	4
valid_sources[0x0f]	27029	1			T23	1		T31	1		T24	1241
valid_sources[0x10]	27443	1			T31	2		T24	1212		T40	1
valid_sources[0x11]	27421	1			T31	3		T24	1129		T44	1
valid_sources[0x12]	27910	1			T28	1		T17	1		T31	1
valid_sources[0x13]	26538	1			T28	3		T17	1		T31	1
valid_sources[0x14]	26699	1			T17	2		T24	1172		T174	1
valid_sources[0x15]	27907	1			T17	1		T24	1185		T40	1
valid_sources[0x16]	27034	1			T28	1		T31	4		T24	1196
valid_sources[0x17]	27578	1			T23	1		T31	1		T24	1244
valid_sources[0x18]	29309	1			T23	2		T24	1250		T142	2
valid_sources[0x19]	27486	1			T31	2		T24	1172		T142	3
valid_sources[0x1a]	28480	1			T31	1		T24	1137		T55	4
valid_sources[0x1b]	26861	1			T3	1		T31	2		T24	1229
valid_sources[0x1c]	27031	1			T28	1		T31	6		T24	1251
valid_sources[0x1d]	27665	1			T23	1		T31	5		T24	1137
valid_sources[0x1e]	26897	1			T4	3		T31	3		T24	1228
valid_sources[0x1f]	27038	1			T31	1		T24	1128		T16	1
valid_sources[0x20]	26915	1			T28	4		T5	1		T31	1
valid_sources[0x21]	27998	1			T28	2		T31	4		T24	1164
valid_sources[0x22]	27551	1			T3	1		T28	2		T17	1
valid_sources[0x23]	27808	1			T28	1		T17	1		T31	1
valid_sources[0x24]	28514	1			T28	1		T31	4		T24	1222
valid_sources[0x25]	27395	1			T17	3		T24	1251		T142	4
valid_sources[0x26]	27455	1			T24	1233		T142	3		T30	1
valid_sources[0x27]	26228	1			T17	1		T31	1		T24	1163
valid_sources[0x28]	26054	1			T17	1		T31	2		T24	1219
valid_sources[0x29]	27717	1			T28	1		T31	1		T24	1129
valid_sources[0x2a]	27067	1			T28	2		T31	2		T24	1195
valid_sources[0x2b]	26183	1			T28	2		T24	1112		T10	1
valid_sources[0x2c]	27060	1			T31	3		T24	1271		T55	1
valid_sources[0x2d]	27155	1			T28	1		T24	1218		T142	3
valid_sources[0x2e]	27814	1			T28	1		T31	2		T24	1178
valid_sources[0x2f]	27192	1			T17	5		T31	2		T24	1221
valid_sources[0x30]	27603	1			T3	1		T31	5		T24	1169
valid_sources[0x31]	27019	1			T31	3		T24	1086		T142	1
valid_sources[0x32]	28157	1			T31	4		T24	1142		T40	2
valid_sources[0x33]	26822	1			T28	3		T23	1		T24	1113
valid_sources[0x34]	27181	1			T27	98		T28	1		T31	2
valid_sources[0x35]	27565	1			T31	3		T24	1158		T39	1
valid_sources[0x36]	27284	1			T17	2		T31	4		T24	1202
valid_sources[0x37]	28568	1			T17	1		T23	2		T24	1167
valid_sources[0x38]	26500	1			T31	1		T24	1141		T142	3
valid_sources[0x39]	26724	1			T28	1		T31	5		T24	1115
valid_sources[0x3a]	26007	1			T31	2		T24	1202		T142	1
valid_sources[0x3b]	26477	1			T17	1		T31	2		T24	1183
valid_sources[0x3c]	27688	1			T28	3		T23	1		T24	1218
valid_sources[0x3d]	27328	1			T31	3		T24	1212		T40	1
valid_sources[0x3e]	27067	1			T31	2		T24	1179		T44	1
valid_sources[0x3f]	27792	1			T28	1		T31	3		T24	1136
valid_sources[0x40]	27238	1			T4	2		T28	1		T24	1145
valid_sources[0x41]	26976	1			T3	1		T31	2		T24	1156
valid_sources[0x42]	26785	1			T3	3		T31	1		T24	1285
valid_sources[0x43]	27226	1			T28	1		T17	1		T23	1
valid_sources[0x44]	28196	1			T17	2		T5	1		T31	1
valid_sources[0x45]	27494	1			T28	1		T31	3		T24	1136
valid_sources[0x46]	28723	1			T31	2		T24	1205		T40	2
valid_sources[0x47]	28606	1			T28	2		T31	4		T24	1230
valid_sources[0x48]	26083	1			T2	382		T31	2		T24	1136
valid_sources[0x49]	27434	1			T31	1		T24	1198		T174	1
valid_sources[0x4a]	26233	1			T3	3		T28	1		T31	1
valid_sources[0x4b]	26453	1			T28	3		T31	3		T24	1163
valid_sources[0x4c]	28818	1			T4	3		T31	3		T24	1151
valid_sources[0x4d]	26417	1			T17	3		T31	2		T24	1167
valid_sources[0x4e]	27794	1			T23	1		T31	3		T24	1280
valid_sources[0x4f]	26492	1			T3	1		T28	2		T31	3
valid_sources[0x50]	26820	1			T28	2		T23	1		T31	2
valid_sources[0x51]	27702	1			T3	6		T31	6		T24	1163
valid_sources[0x52]	26365	1			T31	5		T24	1194		T10	3
valid_sources[0x53]	26868	1			T31	2		T24	1087		T174	2
valid_sources[0x54]	27253	1			T31	6		T24	1162		T44	1
valid_sources[0x55]	28139	1			T31	2		T24	1245		T142	1
valid_sources[0x56]	26883	1			T17	1		T31	4		T24	1108
valid_sources[0x57]	27413	1			T31	3		T24	1199		T16	2
valid_sources[0x58]	27107	1			T31	5		T24	1164		T16	1
valid_sources[0x59]	26752	1			T28	1		T23	3		T31	6
valid_sources[0x5a]	26777	1			T17	1		T24	1170		T40	1
valid_sources[0x5b]	28709	1			T31	4		T24	1152		T174	1
valid_sources[0x5c]	27016	1			T28	1		T31	4		T24	1154
valid_sources[0x5d]	26768	1			T31	1		T24	1236		T40	1
valid_sources[0x5e]	27601	1			T28	1		T24	1136		T142	2
valid_sources[0x5f]	26707	1			T28	2		T31	4		T24	1138
valid_sources[0x60]	26643	1			T4	1		T31	1		T24	1214
valid_sources[0x61]	28348	1			T3	1		T17	3		T31	2
valid_sources[0x62]	27575	1			T31	1		T24	1182		T142	2
valid_sources[0x63]	26961	1			T31	3		T24	1178		T30	1
valid_sources[0x64]	28677	1			T28	3		T31	2		T24	1170
valid_sources[0x65]	26806	1			T17	1		T31	2		T24	1183
valid_sources[0x66]	26424	1			T31	2		T24	1194		T39	2
valid_sources[0x67]	27731	1			T24	1200		T174	1		T55	1
valid_sources[0x68]	29022	1			T31	1		T24	1170		T142	3
valid_sources[0x69]	25566	1			T17	1		T31	5		T24	1137
valid_sources[0x6a]	26430	1			T31	8		T24	1158		T40	1
valid_sources[0x6b]	28319	1			T31	2		T24	1225		T39	1
valid_sources[0x6c]	27920	1			T28	1		T31	2		T24	1271
valid_sources[0x6d]	28016	1			T17	3		T24	1219		T40	2
valid_sources[0x6e]	28582	1			T17	1		T9	137		T31	1
valid_sources[0x6f]	27113	1			T28	1		T31	1		T24	1166
valid_sources[0x70]	27331	1			T17	4		T31	3		T24	1135
valid_sources[0x71]	28030	1			T28	1		T31	2		T24	1181
valid_sources[0x72]	27202	1			T24	1222		T142	1		T30	1
valid_sources[0x73]	26237	1			T17	2		T5	1		T31	5
valid_sources[0x74]	28412	1			T3	1		T31	4		T24	1160
valid_sources[0x75]	27260	1			T28	1		T31	3		T24	1259
valid_sources[0x76]	27331	1			T24	1141		T10	4		T56	1
valid_sources[0x77]	26099	1			T4	1		T17	1		T31	5
valid_sources[0x78]	26476	1			T17	1		T31	8		T24	1104
valid_sources[0x79]	26911	1			T28	1		T31	2		T24	1207
valid_sources[0x7a]	28024	1			T31	1		T24	1218		T174	1
valid_sources[0x7b]	27164	1			T28	1		T31	4		T24	1155
valid_sources[0x7c]	28629	1			T28	1		T31	1		T24	1199
valid_sources[0x7d]	26683	1			T23	2		T31	1		T24	1139
valid_sources[0x7e]	27741	1			T17	1		T31	2		T24	1222
valid_sources[0x7f]	26566	1			T17	1		T31	2		T24	1163
valid_sources[0x80]	28050	1			T28	5		T31	1		T24	1286

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1570871

1

T1

1

T2

39

T3

5

values[0x0]

all_enables

biggest_size

2337105

1

T2

50

T3

8

T4

5

values[0x1]

all_enables

biggest_size

2333636

1

T1

1

T2

45

T3

4