Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2560	1			T2	1		T3	2		T27	1
non_zero_bins[1]	1835	1			T2	4		T9	1		T31	3
zero	8643	1			T2	17		T3	5		T4	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	513	1			T2	1		T3	1		T31	2
uni	3646	1			T2	7		T3	2		T28	1
gen	3917	1			T2	6		T3	2		T4	2
res	796	1			T2	1		T31	2		T24	10
ins	4166	1			T2	7		T3	2		T4	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8849

1

T2

16

T3

6

T4

2

mubi_true

4189

1

T2

6

T3

1

T4

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T17

1

T18

1

T19

1

pass

12988

1

T2

22

T3

7

T4

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	105	1			T31	1		T24	1		T25	3
upd	non_zero_bins[0]	pass	mubi_true	142	1			T31	1		T24	4		T51	1
upd	non_zero_bins[1]	pass	mubi_false	87	1			T24	2		T174	1		T236	1
upd	non_zero_bins[1]	pass	mubi_true	97	1			T2	1		T24	1		T140	1
upd	zero	pass	mubi_false	39	1			T3	1		T24	1		T25	1
upd	zero	pass	mubi_true	43	1			T24	1		T142	1		T26	1
uni	zero	fail	mubi_false	8	1			T18	1		T116	1		T117	1
uni	zero	pass	mubi_false	2661	1			T2	7		T3	2		T28	1
uni	zero	pass	mubi_true	977	1			T31	6		T24	29		T142	2
gen	non_zero_bins[0]	pass	mubi_false	473	1			T3	1		T31	3		T24	9
gen	non_zero_bins[0]	pass	mubi_true	432	1			T31	1		T24	5		T174	1
gen	non_zero_bins[1]	pass	mubi_false	323	1			T24	4		T142	1		T29	9
gen	non_zero_bins[1]	pass	mubi_true	332	1			T2	1		T24	7		T55	1
gen	zero	fail	mubi_false	23	1			T19	1		T60	1		T62	1
gen	zero	pass	mubi_false	1901	1			T2	3		T3	1		T4	2
gen	zero	pass	mubi_true	433	1			T2	2		T17	2		T31	1
res	non_zero_bins[0]	pass	mubi_false	171	1			T31	2		T142	1		T14	2
res	non_zero_bins[0]	pass	mubi_true	184	1			T24	4		T55	1		T142	1
res	non_zero_bins[1]	pass	mubi_false	131	1			T24	4		T25	1		T26	2
res	non_zero_bins[1]	pass	mubi_true	119	1			T10	2		T175	1		T186	2
res	zero	fail	mubi_false	10	1			T61	1		T237	1		T238	1
res	zero	pass	mubi_false	82	1			T24	1		T142	1		T26	1
res	zero	pass	mubi_true	99	1			T2	1		T24	1		T56	2
ins	non_zero_bins[0]	pass	mubi_false	532	1			T2	1		T27	1		T28	1
ins	non_zero_bins[0]	pass	mubi_true	521	1			T3	1		T24	11		T142	1
ins	non_zero_bins[1]	pass	mubi_false	363	1			T2	2		T9	1		T24	5
ins	non_zero_bins[1]	pass	mubi_true	383	1			T31	3		T24	4		T29	1
ins	zero	fail	mubi_false	8	1			T17	1		T98	1		T99	1
ins	zero	fail	mubi_true	1	1			T239	1		-	-		-	-
ins	zero	pass	mubi_false	1932	1			T2	3		T3	1		T5	1
ins	zero	pass	mubi_true	426	1			T2	1		T4	2		T28	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded