Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	244806559	11066794	0	0
boot_gen_cmd_rd_A	244806559	71435	0	0
boot_ins_cmd_rd_A	244806559	81138	0	0
ctrl_rd_A	244806559	71124	0	0
err_code_test_rd_A	244806559	82415	0	0
intr_enable_rd_A	244806559	77678	0	0
max_num_reqs_between_reseeds_rd_A	244806559	72240	0	0
regwen_rd_A	244806559	83876	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	11066794	0	0
T6	1205	0	0	0
T10	1382	0	0	0
T15	1793	0	0	0
T16	2346	0	0	0
T24	905036	501798	0	0
T25	0	226734	0	0
T26	0	230086	0	0
T39	1298	0	0	0
T40	2518	0	0	0
T44	1957	0	0	0
T55	4523	0	0	0
T138	0	21415	0	0
T139	0	165921	0	0
T152	0	351152	0	0
T174	1387	0	0	0
T186	0	17283	0	0
T187	0	379326	0	0
T188	0	208647	0	0
T189	0	115221	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	71435	0	0
T25	603869	3346	0	0
T26	562927	0	0	0
T34	1239	0	0	0
T97	1852	0	0	0
T141	1591	0	0	0
T143	1404	0	0	0
T154	2730	0	0	0
T176	2086	0	0	0
T183	1638	0	0	0
T185	3154	0	0	0
T190	0	6496	0	0
T191	0	3255	0	0
T192	0	11676	0	0
T193	0	886	0	0
T194	0	2203	0	0
T195	0	1132	0	0
T196	0	3964	0	0
T197	0	5075	0	0
T198	0	7347	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	81138	0	0
T25	603869	4141	0	0
T26	562927	0	0	0
T34	1239	0	0	0
T97	1852	0	0	0
T141	1591	0	0	0
T143	1404	0	0	0
T154	2730	0	0	0
T176	2086	0	0	0
T183	1638	0	0	0
T185	3154	0	0	0
T190	0	6650	0	0
T191	0	3929	0	0
T192	0	14090	0	0
T193	0	1093	0	0
T194	0	2340	0	0
T195	0	1179	0	0
T196	0	4544	0	0
T197	0	5732	0	0
T198	0	7923	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	71124	0	0
T14	7224	0	0	0
T18	1959	0	0	0
T20	39214	0	0	0
T25	0	3673	0	0
T29	3503	0	0	0
T30	1646	0	0	0
T36	769	0	0	0
T37	841	0	0	0
T52	2206	0	0	0
T56	6480	0	0	0
T57	0	2	0	0
T70	0	9	0	0
T118	0	3	0	0
T142	27629	5	0	0
T190	0	6012	0	0
T191	0	3354	0	0
T192	0	11829	0	0
T199	0	6	0	0
T200	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	82415	0	0
T25	603869	3929	0	0
T26	562927	0	0	0
T34	1239	0	0	0
T97	1852	0	0	0
T141	1591	0	0	0
T143	1404	0	0	0
T154	2730	0	0	0
T176	2086	0	0	0
T183	1638	0	0	0
T185	3154	0	0	0
T190	0	6934	0	0
T191	0	3769	0	0
T192	0	13798	0	0
T193	0	1168	0	0
T194	0	2459	0	0
T195	0	1085	0	0
T196	0	4415	0	0
T197	0	6197	0	0
T198	0	8432	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	77678	0	0
T14	7224	0	0	0
T18	1959	0	0	0
T20	39214	0	0	0
T25	0	3530	0	0
T29	3503	0	0	0
T30	1646	0	0	0
T36	769	0	0	0
T37	841	0	0	0
T52	2206	0	0	0
T56	6480	0	0	0
T140	0	43	0	0
T142	27629	78	0	0
T190	0	6353	0	0
T191	0	3455	0	0
T192	0	11756	0	0
T200	0	36	0	0
T201	0	66	0	0
T202	0	11	0	0
T203	0	50	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	72240	0	0
T25	603869	3613	0	0
T26	562927	0	0	0
T34	1239	0	0	0
T97	1852	0	0	0
T141	1591	0	0	0
T143	1404	0	0	0
T154	2730	0	0	0
T176	2086	0	0	0
T183	1638	0	0	0
T185	3154	0	0	0
T190	0	6140	0	0
T191	0	3299	0	0
T192	0	11424	0	0
T193	0	875	0	0
T194	0	2260	0	0
T195	0	1072	0	0
T196	0	3969	0	0
T197	0	5189	0	0
T198	0	7122	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244806559	83876	0	0
T25	603869	4211	0	0
T26	562927	0	0	0
T34	1239	0	0	0
T97	1852	0	0	0
T141	1591	0	0	0
T143	1404	0	0	0
T154	2730	0	0	0
T176	2086	0	0	0
T183	1638	0	0	0
T185	3154	0	0	0
T190	0	6779	0	0
T191	0	3759	0	0
T192	0	13737	0	0
T193	0	1059	0	0
T194	0	2483	0	0
T195	0	1098	0	0
T196	0	4543	0	0
T197	0	6184	0	0
T198	0	8406	0	0