Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	642610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5172789

1

T1

27

T2

24

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1537890	1			T1	106		T2	59		T3	151
values[0x0]	1978561	1			T1	9		T2	16		T3	12
values[0x1]	2298948	1			T1	19		T2	10		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	317596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5497803

1

T1

60

T2

41

T3

84

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21282	1			T2	3		T38	2		T40	6
valid_sources[0x01]	22340	1			T1	7		T3	4		T40	5
valid_sources[0x02]	23521	1			T3	2		T5	1		T38	11
valid_sources[0x03]	22729	1			T3	2		T40	4		T37	1
valid_sources[0x04]	22144	1			T2	12		T25	2		T40	3
valid_sources[0x05]	22552	1			T3	1		T24	1		T42	1
valid_sources[0x06]	23101	1			T3	1		T4	2		T40	6
valid_sources[0x07]	23560	1			T1	1		T3	1		T4	1
valid_sources[0x08]	22444	1			T1	4		T40	2		T155	1
valid_sources[0x09]	23227	1			T3	2		T40	4		T37	2
valid_sources[0x0a]	19827	1			T3	1		T4	1		T40	5
valid_sources[0x0b]	23087	1			T3	1		T40	3		T37	2
valid_sources[0x0c]	22710	1			T25	4		T40	6		T42	3
valid_sources[0x0d]	22916	1			T5	2		T40	8		T42	7
valid_sources[0x0e]	22204	1			T2	16		T5	1		T40	3
valid_sources[0x0f]	23095	1			T2	3		T8	1		T25	9
valid_sources[0x10]	24388	1			T1	2		T4	1		T40	3
valid_sources[0x11]	22385	1			T1	1		T3	1		T4	2
valid_sources[0x12]	22462	1			T1	2		T38	1		T40	5
valid_sources[0x13]	22693	1			T4	1		T8	1		T40	1
valid_sources[0x14]	23817	1			T3	1		T5	1		T40	3
valid_sources[0x15]	22472	1			T1	1		T3	1		T4	1
valid_sources[0x16]	23018	1			T8	2		T40	4		T42	2
valid_sources[0x17]	22420	1			T40	8		T185	6		T27	1
valid_sources[0x18]	23702	1			T3	8		T38	4		T40	5
valid_sources[0x19]	22475	1			T1	1		T3	1		T5	1
valid_sources[0x1a]	22881	1			T1	2		T3	2		T24	5
valid_sources[0x1b]	23509	1			T1	3		T40	3		T303	1
valid_sources[0x1c]	21665	1			T1	1		T5	3		T24	1
valid_sources[0x1d]	23071	1			T38	1		T40	6		T42	1
valid_sources[0x1e]	23118	1			T8	1		T40	6		T42	3
valid_sources[0x1f]	21422	1			T5	2		T40	4		T27	1
valid_sources[0x20]	23822	1			T1	1		T24	2		T40	1
valid_sources[0x21]	22248	1			T4	1		T5	1		T12	98
valid_sources[0x22]	20724	1			T3	2		T4	1		T40	1
valid_sources[0x23]	23309	1			T3	2		T8	2		T40	4
valid_sources[0x24]	22803	1			T40	3		T42	4		T33	2
valid_sources[0x25]	23125	1			T3	2		T8	4		T24	6
valid_sources[0x26]	22995	1			T1	3		T5	1		T15	1
valid_sources[0x27]	23157	1			T40	1		T16	1		T42	1
valid_sources[0x28]	23083	1			T3	1		T25	3		T40	4
valid_sources[0x29]	23559	1			T3	3		T40	2		T42	2
valid_sources[0x2a]	21439	1			T40	6		T37	1		T42	2
valid_sources[0x2b]	21883	1			T8	1		T40	8		T155	1
valid_sources[0x2c]	25132	1			T1	1		T3	4		T4	1
valid_sources[0x2d]	23122	1			T40	3		T42	3		T13	1
valid_sources[0x2e]	22073	1			T4	1		T24	6		T40	7
valid_sources[0x2f]	24358	1			T2	4		T8	1		T40	4
valid_sources[0x30]	23185	1			T4	1		T5	2		T40	8
valid_sources[0x31]	23843	1			T3	1		T4	1		T5	1
valid_sources[0x32]	23448	1			T4	1		T38	1		T40	8
valid_sources[0x33]	21095	1			T1	2		T4	2		T5	1
valid_sources[0x34]	20687	1			T3	3		T24	1		T40	7
valid_sources[0x35]	22398	1			T3	4		T4	1		T5	1
valid_sources[0x36]	22603	1			T1	2		T3	1		T5	1
valid_sources[0x37]	23712	1			T3	2		T26	1		T4	1
valid_sources[0x38]	21961	1			T1	1		T5	2		T40	5
valid_sources[0x39]	22965	1			T3	1		T5	1		T40	8
valid_sources[0x3a]	23332	1			T40	6		T37	1		T155	1
valid_sources[0x3b]	23999	1			T40	5		T42	8		T135	1
valid_sources[0x3c]	24734	1			T3	1		T5	3		T40	6
valid_sources[0x3d]	21016	1			T2	4		T38	1		T40	5
valid_sources[0x3e]	21861	1			T1	1		T3	1		T5	1
valid_sources[0x3f]	22543	1			T2	3		T5	1		T40	7
valid_sources[0x40]	24546	1			T38	1		T40	4		T42	1
valid_sources[0x41]	21607	1			T40	4		T42	3		T21	731
valid_sources[0x42]	22212	1			T3	1		T40	3		T27	1
valid_sources[0x43]	22300	1			T5	1		T40	4		T27	1
valid_sources[0x44]	22237	1			T40	2		T42	3		T21	910
valid_sources[0x45]	22604	1			T3	2		T5	1		T24	3
valid_sources[0x46]	22044	1			T4	1		T25	2		T38	2
valid_sources[0x47]	21086	1			T1	1		T2	1		T3	1
valid_sources[0x48]	23854	1			T3	4		T40	3		T16	2
valid_sources[0x49]	24092	1			T24	3		T40	3		T27	2
valid_sources[0x4a]	22877	1			T3	3		T4	1		T15	5
valid_sources[0x4b]	23090	1			T3	3		T40	1		T155	1
valid_sources[0x4c]	21536	1			T6	60		T40	4		T37	2
valid_sources[0x4d]	22153	1			T8	1		T24	3		T40	5
valid_sources[0x4e]	22933	1			T1	1		T40	1		T42	5
valid_sources[0x4f]	21967	1			T4	1		T40	3		T155	1
valid_sources[0x50]	22938	1			T4	1		T5	3		T25	2
valid_sources[0x51]	21677	1			T3	1		T40	2		T37	1
valid_sources[0x52]	24035	1			T26	2		T5	1		T8	4
valid_sources[0x53]	21787	1			T3	1		T5	1		T40	7
valid_sources[0x54]	22743	1			T3	2		T40	3		T37	1
valid_sources[0x55]	22498	1			T1	5		T40	5		T42	4
valid_sources[0x56]	22334	1			T1	3		T3	1		T27	3
valid_sources[0x57]	21448	1			T3	1		T4	1		T8	2
valid_sources[0x58]	22871	1			T1	1		T3	1		T40	11
valid_sources[0x59]	21494	1			T1	1		T4	1		T40	3
valid_sources[0x5a]	23960	1			T1	2		T40	2		T27	1
valid_sources[0x5b]	22235	1			T8	1		T40	5		T42	7
valid_sources[0x5c]	22189	1			T4	1		T40	3		T185	1
valid_sources[0x5d]	22097	1			T1	2		T4	1		T40	2
valid_sources[0x5e]	23672	1			T4	2		T5	1		T8	2
valid_sources[0x5f]	24224	1			T1	1		T3	3		T5	3
valid_sources[0x60]	23180	1			T4	1		T40	5		T27	1
valid_sources[0x61]	21612	1			T3	1		T5	1		T40	5
valid_sources[0x62]	22622	1			T1	7		T8	1		T38	5
valid_sources[0x63]	22551	1			T3	3		T40	2		T16	1
valid_sources[0x64]	21820	1			T3	1		T4	1		T25	2
valid_sources[0x65]	22898	1			T3	2		T40	3		T42	7
valid_sources[0x66]	23171	1			T8	2		T40	1		T185	1
valid_sources[0x67]	25123	1			T2	1		T5	1		T8	1
valid_sources[0x68]	23451	1			T3	3		T40	1		T185	17
valid_sources[0x69]	24492	1			T8	1		T40	2		T37	1
valid_sources[0x6a]	23836	1			T2	3		T3	1		T4	1
valid_sources[0x6b]	20884	1			T1	1		T40	3		T37	1
valid_sources[0x6c]	23271	1			T3	2		T8	1		T24	4
valid_sources[0x6d]	23148	1			T1	1		T3	2		T4	1
valid_sources[0x6e]	22047	1			T3	1		T4	2		T40	1
valid_sources[0x6f]	22981	1			T40	5		T42	8		T33	1
valid_sources[0x70]	21808	1			T40	8		T185	1		T27	1
valid_sources[0x71]	21925	1			T1	1		T3	1		T15	14
valid_sources[0x72]	23724	1			T5	1		T40	7		T37	1
valid_sources[0x73]	21577	1			T1	2		T5	2		T24	3
valid_sources[0x74]	22767	1			T1	1		T8	1		T40	4
valid_sources[0x75]	23485	1			T3	1		T26	1		T5	1
valid_sources[0x76]	23331	1			T5	1		T8	1		T40	2
valid_sources[0x77]	22440	1			T40	2		T42	2		T21	881
valid_sources[0x78]	23697	1			T3	1		T40	4		T42	1
valid_sources[0x79]	21474	1			T4	1		T8	1		T40	4
valid_sources[0x7a]	21402	1			T3	1		T40	5		T27	1
valid_sources[0x7b]	22735	1			T1	2		T3	2		T5	1
valid_sources[0x7c]	21429	1			T4	1		T5	1		T24	6
valid_sources[0x7d]	23310	1			T40	4		T155	1		T42	3
valid_sources[0x7e]	22244	1			T40	6		T37	1		T42	3
valid_sources[0x7f]	23457	1			T3	2		T40	7		T37	1
valid_sources[0x80]	25027	1			T5	1		T40	2		T37	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1301701

1

T1

5

T2

3

T3

6

values[0x0]

all_enables

biggest_size

1937944

1

T1

8

T2

13

T3

12

values[0x1]

all_enables

biggest_size

1933144

1

T1

14

T2

8

T3

15