Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2414	1			T1	1		T12	4		T40	7
non_zero_bins[1]	1752	1			T2	1		T3	1		T12	1
zero	8231	1			T26	2		T5	2		T6	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	479	1			T40	3		T41	1		T62	1
uni	3430	1			T40	12		T41	5		T62	2
gen	3756	1			T26	1		T5	1		T6	1
res	782	1			T12	2		T40	2		T41	2
ins	3950	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8468

1

T1

1

T3

1

T26

1

mubi_true

3929

1

T2

1

T26

1

T15

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T15

1

T8

1

T16

1

pass

12347

1

T1

1

T2

1

T3

1

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	125	1			T30	1		T21	2		T22	2
upd	non_zero_bins[0]	pass	mubi_true	98	1			T40	1		T62	1		T21	1
upd	non_zero_bins[1]	pass	mubi_false	74	1			T40	1		T41	1		T42	1
upd	non_zero_bins[1]	pass	mubi_true	81	1			T185	1		T21	2		T22	2
upd	zero	pass	mubi_false	38	1			T40	1		T22	3		T192	3
upd	zero	pass	mubi_true	63	1			T64	1		T177	1		T22	1
uni	zero	fail	mubi_false	14	1			T16	1		T53	1		T122	1
uni	zero	pass	mubi_false	2492	1			T40	10		T41	5		T62	2
uni	zero	pass	mubi_true	924	1			T40	2		T149	1		T42	9
gen	non_zero_bins[0]	pass	mubi_false	489	1			T40	1		T41	1		T42	2
gen	non_zero_bins[0]	pass	mubi_true	382	1			T12	2		T40	1		T41	1
gen	non_zero_bins[1]	pass	mubi_false	327	1			T40	1		T27	1		T42	1
gen	non_zero_bins[1]	pass	mubi_true	332	1			T40	1		T41	1		T37	2
gen	zero	fail	mubi_false	24	1			T15	1		T8	1		T101	1
gen	zero	pass	mubi_false	1803	1			T26	1		T5	1		T6	1
gen	zero	pass	mubi_true	399	1			T15	2		T8	2		T62	2
res	non_zero_bins[0]	pass	mubi_false	177	1			T12	2		T40	1		T63	2
res	non_zero_bins[0]	pass	mubi_true	188	1			T40	1		T41	1		T37	5
res	non_zero_bins[1]	pass	mubi_false	102	1			T41	1		T63	2		T28	2
res	non_zero_bins[1]	pass	mubi_true	130	1			T21	1		T197	1		T22	2
res	zero	fail	mubi_false	6	1			T68	1		T184	1		T153	1
res	zero	pass	mubi_false	80	1			T42	1		T21	2		T22	1
res	zero	pass	mubi_true	99	1			T42	1		T34	2		T21	2
ins	non_zero_bins[0]	pass	mubi_false	500	1			T1	1		T40	1		T41	1
ins	non_zero_bins[0]	pass	mubi_true	455	1			T40	1		T149	2		T42	7
ins	non_zero_bins[1]	pass	mubi_false	339	1			T3	1		T40	2		T37	1
ins	non_zero_bins[1]	pass	mubi_true	367	1			T2	1		T12	1		T40	1
ins	zero	fail	mubi_false	5	1			T106	1		T107	1		T108	1
ins	zero	fail	mubi_true	1	1			T251	1		-	-		-	-
ins	zero	pass	mubi_false	1873	1			T5	1		T6	1		T15	1
ins	zero	pass	mubi_true	410	1			T26	1		T15	1		T8	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded