Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	199871874	9210423	0	0
boot_gen_cmd_rd_A	199871874	38013	0	0
boot_ins_cmd_rd_A	199871874	42217	0	0
ctrl_rd_A	199871874	38026	0	0
err_code_test_rd_A	199871874	42564	0	0
intr_enable_rd_A	199871874	43481	0	0
max_num_reqs_between_reseeds_rd_A	199871874	38172	0	0
regwen_rd_A	199871874	43340	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	9210423	0	0
T14	987	0	0	0
T21	517121	300197	0	0
T22	434059	160159	0	0
T23	0	159898	0	0
T52	0	397976	0	0
T67	1924	0	0	0
T105	1457	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T190	0	232016	0	0
T191	0	381666	0	0
T192	0	281350	0	0
T193	0	192193	0	0
T194	0	146021	0	0
T195	0	200156	0	0
T196	901	0	0	0
T197	4087	0	0	0
T198	867	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	38013	0	0
T22	434059	2500	0	0
T23	463007	4974	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1445	0	0
T200	0	1284	0	0
T201	0	2503	0	0
T202	0	4154	0	0
T203	0	6476	0	0
T204	0	1855	0	0
T205	0	472	0	0
T206	0	4170	0	0
T207	1830	0	0	0
T208	1656	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	42217	0	0
T22	434059	2736	0	0
T23	463007	5299	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1844	0	0
T200	0	1493	0	0
T201	0	2665	0	0
T202	0	4685	0	0
T203	0	7185	0	0
T204	0	1965	0	0
T205	0	576	0	0
T206	0	4831	0	0
T207	1830	0	0	0
T208	1656	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	38026	0	0
T22	434059	2742	0	0
T23	463007	4814	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T136	0	9	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1681	0	0
T200	0	1316	0	0
T207	1830	0	0	0
T208	1656	0	0	0
T209	0	8	0	0
T210	0	3	0	0
T211	0	7	0	0
T212	0	8	0	0
T213	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	42564	0	0
T22	434059	2702	0	0
T23	463007	5718	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1897	0	0
T200	0	1404	0	0
T201	0	2765	0	0
T202	0	4625	0	0
T203	0	7100	0	0
T204	0	1889	0	0
T205	0	609	0	0
T206	0	4872	0	0
T207	1830	0	0	0
T208	1656	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	43481	0	0
T22	434059	2876	0	0
T23	463007	5769	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1654	0	0
T207	1830	0	0	0
T208	1656	0	0	0
T210	0	41	0	0
T211	0	69	0	0
T212	0	105	0	0
T214	0	11	0	0
T215	0	78	0	0
T216	0	123	0	0
T217	0	65	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	38172	0	0
T22	434059	2512	0	0
T23	463007	4594	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1580	0	0
T200	0	1383	0	0
T201	0	2757	0	0
T202	0	3945	0	0
T203	0	6466	0	0
T204	0	1710	0	0
T205	0	459	0	0
T206	0	4256	0	0
T207	1830	0	0	0
T208	1656	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199871874	43340	0	0
T22	434059	2675	0	0
T23	463007	5504	0	0
T75	1983	0	0	0
T121	2723	0	0	0
T146	1889	0	0	0
T147	4258	0	0	0
T148	13139	0	0	0
T198	867	0	0	0
T199	0	1741	0	0
T200	0	1434	0	0
T201	0	3245	0	0
T202	0	4287	0	0
T203	0	7244	0	0
T204	0	2080	0	0
T205	0	588	0	0
T206	0	4852	0	0
T207	1830	0	0	0
T208	1656	0	0	0