Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	88.46			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T124,T125,T126
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T127,T128,T129
1	0	1	Covered	T4,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	398317860	1426505	0	0
DepthKnown_A	398674254	398386478	0	0
RvalidKnown_A	398674254	398386478	0	0
WreadyKnown_A	398674254	398386478	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	398674254	1509456	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398317860	1426505	0	0
T4	582	189	0	0
T5	328	69	0	0
T6	860	0	0	0
T7	890	421	0	0
T8	4314	552	0	0
T12	13836	10728	0	0
T15	4210	0	0	0
T20	1696	0	0	0
T24	4118	0	0	0
T25	560	0	0	0
T28	0	1499	0	0
T33	0	1472	0	0
T37	0	3414	0	0
T59	0	95	0	0
T63	0	6455	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398674254	398386478	0	0
T1	2666	2538	0	0
T2	8394	8244	0	0
T3	5468	5326	0	0
T4	4848	4522	0	0
T5	1282	898	0	0
T6	4298	3930	0	0
T8	4314	4170	0	0
T15	4210	4034	0	0
T20	1696	1576	0	0
T26	2138	2032	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398674254	398386478	0	0
T1	2666	2538	0	0
T2	8394	8244	0	0
T3	5468	5326	0	0
T4	4848	4522	0	0
T5	1282	898	0	0
T6	4298	3930	0	0
T8	4314	4170	0	0
T15	4210	4034	0	0
T20	1696	1576	0	0
T26	2138	2032	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398674254	398386478	0	0
T1	2666	2538	0	0
T2	8394	8244	0	0
T3	5468	5326	0	0
T4	4848	4522	0	0
T5	1282	898	0	0
T6	4298	3930	0	0
T8	4314	4170	0	0
T15	4210	4034	0	0
T20	1696	1576	0	0
T26	2138	2032	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	398674254	1509456	0	0
T4	4848	3221	0	0
T5	1282	436	0	0
T6	4298	0	0	0
T7	5194	2203	0	0
T8	4314	552	0	0
T12	13836	10728	0	0
T13	0	2304	0	0
T15	4210	0	0	0
T20	1696	0	0	0
T24	4118	0	0	0
T25	1724	0	0	0
T28	0	1499	0	0
T37	0	3414	0	0
T59	0	1410	0	0
T63	0	6455	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T63
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T125,T126,T130
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T128,T131,T132
1	0	1	Covered	T4,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T12,T37,T63

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	199158930	708731	0	0
DepthKnown_A	199337127	199193239	0	0
RvalidKnown_A	199337127	199193239	0	0
WreadyKnown_A	199337127	199193239	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	199337127	750107	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199158930	708731	0	0
T4	291	87	0	0
T5	164	23	0	0
T6	430	0	0	0
T7	445	174	0	0
T8	2157	282	0	0
T12	6918	5340	0	0
T15	2105	0	0	0
T20	848	0	0	0
T24	2059	0	0	0
T25	280	0	0	0
T28	0	759	0	0
T33	0	697	0	0
T37	0	1621	0	0
T59	0	39	0	0
T63	0	3205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	750107	0	0
T4	2424	1619	0	0
T5	641	261	0	0
T6	2149	0	0	0
T7	2597	1036	0	0
T8	2157	282	0	0
T12	6918	5340	0	0
T13	0	1157	0	0
T15	2105	0	0	0
T20	848	0	0	0
T24	2059	0	0	0
T25	862	0	0	0
T28	0	759	0	0
T37	0	1621	0	0
T59	0	690	0	0
T63	0	3205	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T124,T133
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T127,T129,T134
1	0	1	Covered	T4,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	199158930	717774	0	0
DepthKnown_A	199337127	199193239	0	0
RvalidKnown_A	199337127	199193239	0	0
WreadyKnown_A	199337127	199193239	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	199337127	759349	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199158930	717774	0	0
T4	291	102	0	0
T5	164	46	0	0
T6	430	0	0	0
T7	445	247	0	0
T8	2157	270	0	0
T12	6918	5388	0	0
T15	2105	0	0	0
T20	848	0	0	0
T24	2059	0	0	0
T25	280	0	0	0
T28	0	740	0	0
T33	0	775	0	0
T37	0	1793	0	0
T59	0	56	0	0
T63	0	3250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	199193239	0	0
T1	1333	1269	0	0
T2	4197	4122	0	0
T3	2734	2663	0	0
T4	2424	2261	0	0
T5	641	449	0	0
T6	2149	1965	0	0
T8	2157	2085	0	0
T15	2105	2017	0	0
T20	848	788	0	0
T26	1069	1016	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	199337127	759349	0	0
T4	2424	1602	0	0
T5	641	175	0	0
T6	2149	0	0	0
T7	2597	1167	0	0
T8	2157	270	0	0
T12	6918	5388	0	0
T13	0	1147	0	0
T15	2105	0	0	0
T20	848	0	0	0
T24	2059	0	0	0
T25	862	0	0	0
T28	0	740	0	0
T37	0	1793	0	0
T59	0	720	0	0
T63	0	3250	0	0