SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
33.33 | 33.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_error_cg | 33.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 6 | 3 | 33.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_error_test | 9 | 6 | 3 | 33.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 9 | 6 | 3 | 33.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[EdnSfifoRescmdErrTest] | 0 | 1 | 1 | |
auto[EdnSfifoGencmdErrTest] | 0 | 1 | 1 | |
auto[EdnSfifoOutputErrTest] | 0 | 1 | 1 | |
auto[EdnFifoWriteErrTest] | 0 | 1 | 1 | |
auto[EdnFifoReadErrTest] | 0 | 1 | 1 | |
auto[EdnFifoStateErrTest] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[EdnAckSmErrTest] | 660 | 1 | T4 | 1 | T13 | 80 | T5 | 1 | ||||
auto[EdnMainSmErrTest] | 660 | 1 | T4 | 1 | T13 | 80 | T5 | 1 | ||||
auto[EdnCntrErrTest] | 23 | 1 | T5 | 1 | T14 | 1 | T42 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |