Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_sw_cmd_sts_cg 87.50 1 100 1 64 64




Group Instance : edn_sw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance edn_sw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_cmd_ack_cg 2 0 2 100.00 100 1 1 0
cp_cmd_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_reg_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_sts_cg 2 1 1 50.00 100 1 1 0


Summary for Variable cp_cmd_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 25104 1 T1 35 T2 14 T3 491
ack 20260 1 T1 14 T2 9 T3 446



Summary for Variable cp_cmd_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 24282 1 T1 33 T2 13 T3 483
ready 21082 1 T1 16 T2 10 T3 454



Summary for Variable cp_cmd_reg_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_reg_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 475 1 T3 9 T22 4 T23 7
ready 44889 1 T1 49 T2 23 T3 928



Summary for Variable cp_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_cmd_sts_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
error 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
success 45364 1 T1 49 T2 23 T3 937

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%