| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1686 | 1 | T2 | 1 | T3 | 33 | T20 | 1 | ||||
| auto[2] | 72332 | 1 | T2 | 4 | T3 | 132 | T20 | 4 | ||||
| auto[3] | 71659 | 1 | T2 | 4 | T3 | 132 | T20 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 142 | 1 | T20 | 1 | T24 | 1 | T8 | 1 | ||||
| auto[2] | 5160 | 1 | T20 | 16 | T4 | 1 | T24 | 34 | ||||
| auto[3] | 5142 | 1 | T20 | 16 | T24 | 34 | T8 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 119 | 1 | T20 | 1 | T25 | 1 | T8 | 1 | ||||
| auto[2] | 3424 | 1 | T20 | 46 | T25 | 4 | T6 | 1 | ||||
| auto[3] | 3410 | 1 | T20 | 46 | T25 | 4 | T8 | 13 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 103 | 1 | T26 | 1 | T8 | 1 | T27 | 1 | ||||
| auto[2] | 1684 | 1 | T26 | 4 | T8 | 160 | T27 | 4 | ||||
| auto[3] | 1679 | 1 | T26 | 4 | T8 | 160 | T27 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 105 | 1 | T28 | 1 | T8 | 1 | T29 | 1 | ||||
| auto[2] | 2771 | 1 | T28 | 4 | T8 | 4 | T29 | 8 | ||||
| auto[3] | 2769 | 1 | T28 | 4 | T8 | 4 | T29 | 8 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 94 | 1 | T20 | 1 | T26 | 1 | T37 | 1 | ||||
| auto[2] | 2261 | 1 | T20 | 27 | T14 | 1 | T26 | 4 | ||||
| auto[3] | 2255 | 1 | T20 | 27 | T26 | 4 | T37 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 83 | 1 | T20 | 1 | T8 | 1 | T27 | 1 | ||||
| auto[2] | 3255 | 1 | T20 | 27 | T8 | 4 | T27 | 7 | ||||
| auto[3] | 3252 | 1 | T20 | 27 | T8 | 4 | T27 | 7 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |