Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2451	1			T1	3		T2	1		T3	38
non_zero_bins[1]	1670	1			T1	2		T2	1		T3	32
zero	7948	1			T1	3		T2	3		T3	157

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	450	1			T1	1		T3	9		T20	1
uni	3353	1			T1	2		T2	2		T3	74
gen	3655	1			T1	2		T2	1		T3	62
res	761	1			T1	1		T3	8		T32	1
ins	3850	1			T1	2		T2	2		T3	74

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8196

1

T1

4

T2

3

T3

171

mubi_true

3873

1

T1

4

T2

2

T3

56

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T15

1

T16

1

T17

1

pass

12019

1

T1

8

T2

5

T3

227

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	120	1			T3	5		T22	2		T23	5
upd	non_zero_bins[0]	pass	mubi_true	102	1			T3	2		T20	1		T21	1
upd	non_zero_bins[1]	pass	mubi_false	79	1			T3	1		T23	2		T194	1
upd	non_zero_bins[1]	pass	mubi_true	70	1			T22	2		T23	1		T127	1
upd	zero	pass	mubi_false	47	1			T3	1		T128	2		T179	1
upd	zero	pass	mubi_true	32	1			T1	1		T22	3		T27	1
uni	zero	fail	mubi_false	11	1			T107	1		T108	1		T109	1
uni	zero	pass	mubi_false	2414	1			T1	2		T2	2		T3	58
uni	zero	pass	mubi_true	928	1			T3	16		T22	9		T23	22
gen	non_zero_bins[0]	pass	mubi_false	434	1			T1	1		T3	7		T21	1
gen	non_zero_bins[0]	pass	mubi_true	440	1			T3	3		T20	1		T22	4
gen	non_zero_bins[1]	pass	mubi_false	327	1			T3	7		T22	7		T23	7
gen	non_zero_bins[1]	pass	mubi_true	264	1			T1	1		T2	1		T3	4
gen	zero	fail	mubi_false	22	1			T15	1		T17	1		T58	1
gen	zero	pass	mubi_false	1746	1			T3	36		T20	1		T31	1
gen	zero	pass	mubi_true	422	1			T3	5		T4	1		T22	1
res	non_zero_bins[0]	pass	mubi_false	191	1			T3	1		T22	1		T23	5
res	non_zero_bins[0]	pass	mubi_true	164	1			T1	1		T3	4		T22	1
res	non_zero_bins[1]	pass	mubi_false	105	1			T3	1		T22	1		T23	2
res	non_zero_bins[1]	pass	mubi_true	142	1			T3	1		T22	4		T23	1
res	zero	fail	mubi_false	11	1			T16	1		T130	1		T228	1
res	zero	pass	mubi_false	72	1			T3	1		T22	1		T23	2
res	zero	pass	mubi_true	76	1			T32	1		T22	1		T8	2
ins	non_zero_bins[0]	pass	mubi_false	497	1			T1	1		T2	1		T3	7
ins	non_zero_bins[0]	pass	mubi_true	503	1			T3	9		T22	5		T23	12
ins	non_zero_bins[1]	pass	mubi_false	321	1			T3	8		T32	1		T30	1
ins	non_zero_bins[1]	pass	mubi_true	362	1			T1	1		T3	10		T22	3
ins	zero	fail	mubi_false	6	1			T93	1		T94	1		T95	1
ins	zero	pass	mubi_false	1793	1			T3	38		T4	1		T31	1
ins	zero	pass	mubi_true	368	1			T2	1		T3	2		T20	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded