Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	220829218	10188499	0	0
boot_gen_cmd_rd_A	220829218	55207	0	0
boot_ins_cmd_rd_A	220829218	61124	0	0
ctrl_rd_A	220829218	54630	0	0
err_code_test_rd_A	220829218	61923	0	0
intr_enable_rd_A	220829218	61687	0	0
max_num_reqs_between_reseeds_rd_A	220829218	55960	0	0
regwen_rd_A	220829218	63590	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	10188499	0	0
T3	981441	548291	0	0
T4	2865	0	0	0
T5	3312	0	0	0
T13	17980	0	0	0
T20	2131	0	0	0
T21	1581	0	0	0
T22	0	173301	0	0
T23	0	251921	0	0
T25	872	0	0	0
T30	2468	0	0	0
T31	3879	0	0	0
T32	1471	0	0	0
T128	0	312633	0	0
T176	0	113932	0	0
T177	0	353820	0	0
T178	0	213511	0	0
T179	0	104729	0	0
T180	0	627759	0	0
T181	0	81017	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	55207	0	0
T14	1793	0	0	0
T23	679879	4174	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1489	0	0
T183	0	3887	0	0
T184	0	7250	0	0
T185	0	3088	0	0
T186	0	518	0	0
T187	0	11017	0	0
T188	0	7425	0	0
T189	0	409	0	0
T190	0	2655	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	61124	0	0
T14	1793	0	0	0
T23	679879	4530	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1672	0	0
T183	0	4510	0	0
T184	0	7831	0	0
T185	0	3522	0	0
T186	0	568	0	0
T187	0	12541	0	0
T188	0	8300	0	0
T189	0	567	0	0
T190	0	2997	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	54630	0	0
T14	1793	0	0	0
T23	679879	3737	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T61	0	5	0	0
T93	0	3	0	0
T120	0	4	0	0
T127	0	7	0	0
T131	0	3	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1593	0	0
T191	0	3	0	0
T192	0	2	0	0
T193	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	61923	0	0
T14	1793	0	0	0
T23	679879	4387	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1738	0	0
T183	0	4578	0	0
T184	0	7738	0	0
T185	0	3726	0	0
T186	0	549	0	0
T187	0	12513	0	0
T188	0	8778	0	0
T189	0	581	0	0
T190	0	2811	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	61687	0	0
T1	8028	83	0	0
T2	2771	0	0	0
T3	981441	0	0	0
T4	2865	0	0	0
T5	3312	0	0	0
T13	17980	0	0	0
T20	2131	0	0	0
T21	1581	0	0	0
T23	0	4400	0	0
T30	2468	0	0	0
T32	1471	0	0	0
T127	0	54	0	0
T142	0	6	0	0
T182	0	1440	0	0
T183	0	4243	0	0
T184	0	7834	0	0
T192	0	35	0	0
T194	0	63	0	0
T195	0	18	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	55960	0	0
T14	1793	0	0	0
T23	679879	3913	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1287	0	0
T183	0	4179	0	0
T184	0	6512	0	0
T185	0	3262	0	0
T186	0	460	0	0
T187	0	11018	0	0
T188	0	7257	0	0
T189	0	520	0	0
T190	0	2758	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220829218	63590	0	0
T14	1793	0	0	0
T23	679879	4481	0	0
T24	1839	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T37	2593	0	0	0
T39	1576	0	0	0
T51	641	0	0	0
T163	1326	0	0	0
T164	2257	0	0	0
T182	0	1696	0	0
T183	0	4569	0	0
T184	0	8154	0	0
T185	0	3877	0	0
T186	0	487	0	0
T187	0	12447	0	0
T188	0	8461	0	0
T189	0	473	0	0
T190	0	2890	0	0