Unified Coverage Report :: Module :: prim_generic_buf

Module : prim_generic_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[6].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[6].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[6].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[6].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[7].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[7].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[7].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[7].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[8].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[8].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[8].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[8].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[9].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[9].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[9].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[9].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[10].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[10].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[10].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[10].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[11].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[11].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[11].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[11].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[12].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[12].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[12].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[12].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[13].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[13].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[13].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[13].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[14].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[14].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[14].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[14].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[15].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[15].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[15].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[15].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[16].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[16].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[16].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[16].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[17].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[17].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[17].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[17].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[18].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[18].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[18].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[18].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[19].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[19].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[19].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[19].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1