Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	93.75	100.00	75.00			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T110,T111
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T112,T113,T114
1	0	1	Covered	T4,T5,T14
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	440304654	893850	0	0
DepthKnown_A	440670380	440383620	0	0
RvalidKnown_A	440670380	440383620	0	0
WreadyKnown_A	440670380	440383620	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	440670380	975861	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440304654	893850	0	0
T5	646	203	0	0
T6	0	65	0	0
T7	0	188	0	0
T8	0	1859	0	0
T9	0	1408	0	0
T12	0	3196	0	0
T14	194	0	0	0
T22	850270	0	0	0
T23	1359758	0	0	0
T25	1744	0	0	0
T26	4956	0	0	0
T28	1788	0	0	0
T30	4936	0	0	0
T31	7758	0	0	0
T39	3152	0	0	0
T52	0	87	0	0
T53	0	8197	0	0
T56	0	2204	0	0
T57	0	3877	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440670380	440383620	0	0
T1	16056	15382	0	0
T2	5542	5346	0	0
T3	1962882	1962862	0	0
T4	5730	5466	0	0
T5	6624	6278	0	0
T13	35960	20432	0	0
T20	4262	4068	0	0
T21	3162	3014	0	0
T30	4936	4770	0	0
T32	2942	2762	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440670380	440383620	0	0
T1	16056	15382	0	0
T2	5542	5346	0	0
T3	1962882	1962862	0	0
T4	5730	5466	0	0
T5	6624	6278	0	0
T13	35960	20432	0	0
T20	4262	4068	0	0
T21	3162	3014	0	0
T30	4936	4770	0	0
T32	2942	2762	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440670380	440383620	0	0
T1	16056	15382	0	0
T2	5542	5346	0	0
T3	1962882	1962862	0	0
T4	5730	5466	0	0
T5	6624	6278	0	0
T13	35960	20432	0	0
T20	4262	4068	0	0
T21	3162	3014	0	0
T30	4936	4770	0	0
T32	2942	2762	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	440670380	975861	0	0
T4	5730	2292	0	0
T5	6624	3687	0	0
T6	0	1054	0	0
T7	0	1237	0	0
T8	0	1859	0	0
T12	0	3196	0	0
T13	35960	0	0	0
T14	3586	220	0	0
T22	850270	0	0	0
T23	1359758	0	0	0
T25	1744	0	0	0
T30	4936	0	0	0
T31	7758	0	0	0
T32	2942	0	0	0
T42	0	304	0	0
T51	0	322	0	0
T52	0	854	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T113,T114,T115
1	0	1	Covered	T4,T5,T14
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220152327	451203	0	0
DepthKnown_A	220335190	220191810	0	0
RvalidKnown_A	220335190	220191810	0	0
WreadyKnown_A	220335190	220191810	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220335190	492172	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220152327	451203	0	0
T5	323	95	0	0
T6	0	36	0	0
T7	0	97	0	0
T8	0	984	0	0
T9	0	715	0	0
T12	0	1607	0	0
T14	97	0	0	0
T22	425135	0	0	0
T23	679879	0	0	0
T25	872	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T30	2468	0	0	0
T31	3879	0	0	0
T39	1576	0	0	0
T52	0	50	0	0
T53	0	4104	0	0
T56	0	1153	0	0
T57	0	1980	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	492172	0	0
T4	2865	1144	0	0
T5	3312	1832	0	0
T6	0	532	0	0
T7	0	641	0	0
T8	0	984	0	0
T12	0	1607	0	0
T13	17980	0	0	0
T14	1793	109	0	0
T22	425135	0	0	0
T23	679879	0	0	0
T25	872	0	0	0
T30	2468	0	0	0
T31	3879	0	0	0
T32	1471	0	0	0
T42	0	147	0	0
T51	0	158	0	0
T52	0	433	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T116,T117,T62
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T110,T111
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T112,T118
1	0	1	Covered	T4,T5,T14
1	1	0	Not Covered
1	1	1	Covered	T8,T12,T53

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220152327	442647	0	0
DepthKnown_A	220335190	220191810	0	0
RvalidKnown_A	220335190	220191810	0	0
WreadyKnown_A	220335190	220191810	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220335190	483689	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220152327	442647	0	0
T5	323	108	0	0
T6	0	29	0	0
T7	0	91	0	0
T8	0	875	0	0
T9	0	693	0	0
T12	0	1589	0	0
T14	97	0	0	0
T22	425135	0	0	0
T23	679879	0	0	0
T25	872	0	0	0
T26	2478	0	0	0
T28	894	0	0	0
T30	2468	0	0	0
T31	3879	0	0	0
T39	1576	0	0	0
T52	0	37	0	0
T53	0	4093	0	0
T56	0	1051	0	0
T57	0	1897	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	220191810	0	0
T1	8028	7691	0	0
T2	2771	2673	0	0
T3	981441	981431	0	0
T4	2865	2733	0	0
T5	3312	3139	0	0
T13	17980	10216	0	0
T20	2131	2034	0	0
T21	1581	1507	0	0
T30	2468	2385	0	0
T32	1471	1381	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220335190	483689	0	0
T4	2865	1148	0	0
T5	3312	1855	0	0
T6	0	522	0	0
T7	0	596	0	0
T8	0	875	0	0
T12	0	1589	0	0
T13	17980	0	0	0
T14	1793	111	0	0
T22	425135	0	0	0
T23	679879	0	0	0
T25	872	0	0	0
T30	2468	0	0	0
T31	3879	0	0	0
T32	1471	0	0	0
T42	0	157	0	0
T51	0	164	0	0
T52	0	421	0	0