Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	706386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5623737

1

T1

28

T2

46

T3

93

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1679033	1			T1	449		T2	555		T3	251
values[0x0]	2147218	1			T1	12		T2	25		T3	7
values[0x1]	2503872	1			T1	14		T2	17		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349671	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5980452

1

T1

184

T2

214

T3

156

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24925	1			T1	3		T5	1		T34	1
valid_sources[0x01]	25294	1			T1	1		T27	3		T19	1
valid_sources[0x02]	23991	1			T2	1		T12	1		T27	3
valid_sources[0x03]	26516	1			T1	2		T12	4		T133	2
valid_sources[0x04]	25744	1			T1	1		T34	3		T23	715
valid_sources[0x05]	24691	1			T1	1		T2	2		T34	4
valid_sources[0x06]	24252	1			T145	1		T132	1		T23	120
valid_sources[0x07]	24494	1			T2	4		T27	5		T5	1
valid_sources[0x08]	24434	1			T1	2		T2	5		T133	1
valid_sources[0x09]	25232	1			T1	1		T12	1		T23	487
valid_sources[0x0a]	23827	1			T2	8		T12	3		T34	8
valid_sources[0x0b]	24251	1			T1	1		T27	1		T133	1
valid_sources[0x0c]	25410	1			T1	4		T34	5		T88	2
valid_sources[0x0d]	23729	1			T1	2		T2	3		T34	5
valid_sources[0x0e]	24308	1			T1	1		T2	3		T133	1
valid_sources[0x0f]	25017	1			T1	5		T2	3		T27	1
valid_sources[0x10]	24597	1			T17	6		T5	3		T19	1
valid_sources[0x11]	25925	1			T1	1		T2	14		T145	1
valid_sources[0x12]	24009	1			T1	4		T2	2		T12	1
valid_sources[0x13]	24979	1			T1	1		T12	1		T11	113
valid_sources[0x14]	25034	1			T132	1		T32	2		T23	170
valid_sources[0x15]	27162	1			T1	2		T2	1		T27	1
valid_sources[0x16]	23632	1			T1	1		T2	9		T133	1
valid_sources[0x17]	25771	1			T1	2		T2	5		T133	2
valid_sources[0x18]	24103	1			T1	4		T145	1		T34	8
valid_sources[0x19]	26286	1			T1	2		T2	16		T133	1
valid_sources[0x1a]	25795	1			T2	8		T12	2		T109	1
valid_sources[0x1b]	24569	1			T1	2		T2	14		T18	8
valid_sources[0x1c]	24551	1			T1	1		T19	2		T34	3
valid_sources[0x1d]	25792	1			T1	5		T2	5		T18	7
valid_sources[0x1e]	23754	1			T5	1		T19	3		T34	3
valid_sources[0x1f]	25904	1			T1	1		T2	5		T34	4
valid_sources[0x20]	23097	1			T133	1		T19	1		T34	3
valid_sources[0x21]	23494	1			T1	2		T145	1		T19	1
valid_sources[0x22]	24265	1			T1	4		T12	5		T19	1
valid_sources[0x23]	24984	1			T1	1		T27	2		T34	3
valid_sources[0x24]	25925	1			T34	2		T32	3		T23	554
valid_sources[0x25]	26700	1			T1	4		T2	1		T12	2
valid_sources[0x26]	23838	1			T1	1		T133	1		T132	1
valid_sources[0x27]	24887	1			T1	3		T145	1		T19	1
valid_sources[0x28]	26462	1			T34	2		T32	6		T23	726
valid_sources[0x29]	26621	1			T2	3		T27	2		T109	1
valid_sources[0x2a]	24227	1			T1	3		T2	4		T109	1
valid_sources[0x2b]	25767	1			T1	1		T2	14		T34	2
valid_sources[0x2c]	23214	1			T1	1		T109	1		T34	1
valid_sources[0x2d]	24440	1			T1	6		T2	4		T34	7
valid_sources[0x2e]	25197	1			T2	2		T12	1		T27	3
valid_sources[0x2f]	25534	1			T1	3		T12	6		T17	2
valid_sources[0x30]	24752	1			T1	4		T2	9		T27	1
valid_sources[0x31]	23152	1			T1	1		T109	1		T34	2
valid_sources[0x32]	25681	1			T1	3		T31	1		T19	1
valid_sources[0x33]	25579	1			T1	2		T2	2		T12	2
valid_sources[0x34]	25292	1			T2	2		T5	1		T19	1
valid_sources[0x35]	23334	1			T31	14		T133	1		T88	1
valid_sources[0x36]	23707	1			T1	4		T2	3		T5	1
valid_sources[0x37]	23080	1			T1	6		T2	9		T5	3
valid_sources[0x38]	25056	1			T12	3		T27	7		T10	10
valid_sources[0x39]	24498	1			T1	2		T34	5		T132	1
valid_sources[0x3a]	24797	1			T17	1		T34	5		T132	1
valid_sources[0x3b]	24099	1			T1	6		T145	2		T19	2
valid_sources[0x3c]	23347	1			T1	2		T2	1		T12	3
valid_sources[0x3d]	24293	1			T34	2		T32	2		T23	530
valid_sources[0x3e]	24599	1			T1	2		T2	3		T17	2
valid_sources[0x3f]	25939	1			T1	2		T5	1		T34	6
valid_sources[0x40]	22989	1			T34	2		T132	1		T23	275
valid_sources[0x41]	24107	1			T12	1		T27	2		T109	1
valid_sources[0x42]	23098	1			T1	3		T2	9		T34	4
valid_sources[0x43]	24781	1			T1	1		T34	5		T23	731
valid_sources[0x44]	24637	1			T1	1		T2	17		T27	2
valid_sources[0x45]	23140	1			T1	5		T145	2		T34	1
valid_sources[0x46]	23858	1			T1	1		T132	1		T23	375
valid_sources[0x47]	25291	1			T1	1		T132	1		T23	360
valid_sources[0x48]	26008	1			T1	1		T2	4		T22	86
valid_sources[0x49]	24718	1			T1	3		T2	7		T133	1
valid_sources[0x4a]	24183	1			T1	3		T133	1		T16	5
valid_sources[0x4b]	24260	1			T1	2		T17	2		T34	2
valid_sources[0x4c]	24108	1			T1	2		T2	1		T12	2
valid_sources[0x4d]	25216	1			T1	6		T2	3		T12	2
valid_sources[0x4e]	23744	1			T1	1		T34	7		T132	1
valid_sources[0x4f]	24090	1			T145	1		T34	15		T88	1
valid_sources[0x50]	26365	1			T2	3		T12	3		T132	1
valid_sources[0x51]	25934	1			T2	2		T5	1		T133	1
valid_sources[0x52]	23828	1			T1	2		T27	2		T5	1
valid_sources[0x53]	24556	1			T1	3		T2	2		T145	1
valid_sources[0x54]	24406	1			T2	22		T5	2		T34	13
valid_sources[0x55]	26957	1			T1	1		T2	6		T18	2
valid_sources[0x56]	26347	1			T1	1		T12	1		T19	1
valid_sources[0x57]	23754	1			T1	1		T109	2		T132	1
valid_sources[0x58]	24154	1			T34	4		T23	763		T179	2
valid_sources[0x59]	22777	1			T1	3		T2	5		T109	1
valid_sources[0x5a]	23850	1			T1	3		T31	31		T132	1
valid_sources[0x5b]	24446	1			T2	6		T12	1		T34	8
valid_sources[0x5c]	24541	1			T1	4		T34	3		T132	1
valid_sources[0x5d]	25672	1			T1	6		T2	1		T12	1
valid_sources[0x5e]	25820	1			T1	4		T88	1		T23	134
valid_sources[0x5f]	23484	1			T1	1		T34	5		T88	1
valid_sources[0x60]	27867	1			T1	1		T2	2		T109	1
valid_sources[0x61]	24331	1			T1	2		T2	3		T133	1
valid_sources[0x62]	26683	1			T1	6		T34	6		T132	2
valid_sources[0x63]	24523	1			T1	2		T12	2		T27	8
valid_sources[0x64]	24753	1			T1	2		T2	1		T12	3
valid_sources[0x65]	23564	1			T2	9		T5	2		T133	1
valid_sources[0x66]	25722	1			T1	1		T133	1		T34	3
valid_sources[0x67]	23414	1			T1	1		T34	1		T132	1
valid_sources[0x68]	25556	1			T1	2		T31	6		T34	3
valid_sources[0x69]	23209	1			T1	1		T2	17		T9	89
valid_sources[0x6a]	27225	1			T1	1		T133	1		T34	3
valid_sources[0x6b]	25229	1			T1	6		T27	1		T133	2
valid_sources[0x6c]	27462	1			T1	1		T2	3		T27	3
valid_sources[0x6d]	24813	1			T1	3		T5	2		T34	2
valid_sources[0x6e]	23740	1			T1	1		T2	17		T133	1
valid_sources[0x6f]	25116	1			T12	2		T5	1		T145	1
valid_sources[0x70]	23422	1			T1	1		T5	1		T88	2
valid_sources[0x71]	23968	1			T5	1		T145	1		T19	1
valid_sources[0x72]	24523	1			T2	18		T31	9		T19	1
valid_sources[0x73]	25540	1			T2	9		T34	1		T23	109
valid_sources[0x74]	25840	1			T1	5		T2	1		T12	1
valid_sources[0x75]	25580	1			T27	8		T34	4		T23	896
valid_sources[0x76]	23652	1			T1	1		T17	2		T18	9
valid_sources[0x77]	26218	1			T1	2		T12	2		T34	1
valid_sources[0x78]	24614	1			T1	4		T23	755		T48	1
valid_sources[0x79]	23767	1			T17	3		T133	1		T19	1
valid_sources[0x7a]	24036	1			T1	1		T2	1		T5	2
valid_sources[0x7b]	25310	1			T1	2		T10	13		T34	2
valid_sources[0x7c]	24419	1			T1	1		T34	1		T132	1
valid_sources[0x7d]	26459	1			T1	2		T12	2		T34	2
valid_sources[0x7e]	25126	1			T1	2		T133	2		T34	2
valid_sources[0x7f]	25181	1			T1	3		T34	1		T88	1
valid_sources[0x80]	23291	1			T1	2		T2	1		T34	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1415753

1

T1

5

T2

8

T3

85

values[0x0]

all_enables

biggest_size

2103486

1

T1

11

T2

22

T3

5

values[0x1]

all_enables

biggest_size

2104498

1

T1

12

T2

16

T3

3