Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2678	1			T2	1		T22	1		T9	1
non_zero_bins[1]	1922	1			T1	1		T2	2		T22	1
zero	9067	1			T1	3		T2	5		T22	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	499	1			T22	1		T27	1		T34	1
uni	3865	1			T1	1		T2	3		T22	1
gen	4086	1			T1	1		T2	2		T22	1
res	852	1			T9	2		T12	2		T10	3
ins	4365	1			T1	2		T2	3		T22	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9381

1

T1

2

T2

4

T22

2

mubi_true

4286

1

T1

2

T2

4

T22

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T17

1

T18

1

T19

1

pass

13617

1

T1

4

T2

8

T22

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	120	1			T23	2		T24	2		T25	1
upd	non_zero_bins[0]	pass	mubi_true	112	1			T22	1		T23	1		T35	1
upd	non_zero_bins[1]	pass	mubi_false	84	1			T34	1		T23	2		T24	6
upd	non_zero_bins[1]	pass	mubi_true	90	1			T27	1		T23	1		T24	1
upd	zero	pass	mubi_false	44	1			T25	1		T227	1		T130	1
upd	zero	pass	mubi_true	49	1			T25	1		T174	1		T130	1
uni	zero	fail	mubi_false	8	1			T17	1		T105	1		T106	1
uni	zero	pass	mubi_false	2804	1			T1	1		T2	2		T22	1
uni	zero	pass	mubi_true	1053	1			T2	1		T109	1		T145	1
gen	non_zero_bins[0]	pass	mubi_false	517	1			T133	1		T132	1		T23	5
gen	non_zero_bins[0]	pass	mubi_true	462	1			T12	6		T27	1		T10	2
gen	non_zero_bins[1]	pass	mubi_false	362	1			T9	2		T138	1		T34	3
gen	non_zero_bins[1]	pass	mubi_true	299	1			T2	1		T33	1		T23	1
gen	zero	fail	mubi_false	25	1			T18	1		T19	1		T48	1
gen	zero	pass	mubi_false	1996	1			T1	1		T4	1		T17	1
gen	zero	pass	mubi_true	425	1			T2	1		T22	1		T27	1
res	non_zero_bins[0]	pass	mubi_false	189	1			T12	2		T23	1		T114	1
res	non_zero_bins[0]	pass	mubi_true	196	1			T10	3		T138	1		T23	2
res	non_zero_bins[1]	pass	mubi_false	142	1			T9	2		T23	2		T35	2
res	non_zero_bins[1]	pass	mubi_true	164	1			T31	1		T34	2		T59	2
res	zero	fail	mubi_false	6	1			T49	1		T141	1		T228	1
res	zero	pass	mubi_false	78	1			T23	1		T115	2		T131	1
res	zero	pass	mubi_true	77	1			T33	1		T129	2		T24	2
ins	non_zero_bins[0]	pass	mubi_false	549	1			T34	1		T32	1		T23	9
ins	non_zero_bins[0]	pass	mubi_true	533	1			T2	1		T9	1		T12	1
ins	non_zero_bins[1]	pass	mubi_false	401	1			T2	1		T22	1		T26	1
ins	non_zero_bins[1]	pass	mubi_true	380	1			T1	1		T138	1		T31	1
ins	zero	fail	mubi_false	11	1			T88	1		T89	1		T90	1
ins	zero	pass	mubi_false	2045	1			T2	1		T4	1		T17	2
ins	zero	pass	mubi_true	446	1			T1	1		T27	1		T17	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded