Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T104,T146,T147
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T11,T81,T70
DataWait->Error	99	Covered	T16,T46,T37
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1555869224	866652	0	0
FpvSecCmErrorStEscalate_A	1555869224	872581	0	0
u_state_regs_A	1555832736	1554739084	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555869224	866652	0	0
T3	117250	33866	0	0
T4	2548	0	0	0
T6	0	3226	0	0
T7	0	2603	0	0
T9	30170	0	0	0
T12	21028	0	0	0
T15	0	2506	0	0
T16	0	3654	0	0
T17	14014	0	0	0
T18	13391	0	0	0
T22	12705	0	0	0
T26	17871	0	0	0
T27	10199	0	0	0
T36	0	2905	0	0
T37	0	2744	0	0
T43	8344	0	0	0
T46	0	2156	0	0
T87	0	4150	0	0
T108	0	2827	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555869224	872581	0	0
T3	117250	34496	0	0
T4	2548	0	0	0
T6	0	3233	0	0
T7	0	2610	0	0
T9	30170	0	0	0
T12	21028	0	0	0
T15	0	2513	0	0
T16	0	3661	0	0
T17	14014	0	0	0
T18	13391	0	0	0
T22	12705	0	0	0
T26	17871	0	0	0
T27	10199	0	0	0
T36	0	2912	0	0
T37	0	2751	0	0
T43	8344	0	0	0
T46	0	2163	0	0
T87	0	4157	0	0
T108	0	2834	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555832736	1554739084	0	0
T1	14665	14301	0	0
T2	37541	36953	0	0
T3	117250	64960	0	0
T4	2534	1659	0	0
T9	30170	29519	0	0
T12	21028	20580	0	0
T17	14014	13496	0	0
T22	12705	12166	0	0
T26	17871	17444	0	0
T27	10199	9730	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T150,T151,T152
DataWait->Error	99	Covered	T16,T46,T41
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T8,T39
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T36,T37

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	122436	0	0
FpvSecCmErrorStEscalate_A	222267032	123283	0	0
u_state_regs_A	222230544	222074308	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	122436	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	418	0	0
T7	0	329	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	550	0	0
T108	0	361	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	123283	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	419	0	0
T7	0	330	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	551	0	0
T108	0	362	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222230544	222074308	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	350	225	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T26
DataWait	75	Covered	T1,T2,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T26
DataWait->AckPls	80	Covered	T1,T2,T26
DataWait->Disabled	107	Covered	T70,T153,T154
DataWait->Error	99	Covered	T155
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T26
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T26
Idle	-	1	0	-	Covered	T1,T2,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T26
DataWait	-	-	-	0	Covered	T1,T2,T26
AckPls	-	-	-	-	Covered	T1,T2,T26
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T22,T27
DataWait	75	Covered	T2,T22,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T22,T27
DataWait->AckPls	80	Covered	T2,T22,T27
DataWait->Disabled	107	Covered	T156,T157,T158
DataWait->Error	99	Covered	T76,T159,T160
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T22,T27
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T22,T27
Idle	-	1	0	-	Covered	T2,T22,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T22,T27
DataWait	-	-	-	0	Covered	T2,T22,T27
AckPls	-	-	-	-	Covered	T2,T22,T27
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T26
DataWait	75	Covered	T1,T2,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T26
DataWait->AckPls	80	Covered	T1,T2,T26
DataWait->Disabled	107	Covered	T11,T81,T53
DataWait->Error	99	Covered	T87,T47,T51
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T26
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T26
Idle	-	1	0	-	Covered	T1,T2,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T26
DataWait	-	-	-	0	Covered	T1,T2,T26
AckPls	-	-	-	-	Covered	T1,T2,T26
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T52,T71,T161
DataWait->Error	99	Covered	T77,T162,T163
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T22,T12
DataWait	75	Covered	T1,T22,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T104
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T22,T12
DataWait->AckPls	80	Covered	T1,T22,T12
DataWait->Disabled	107	Covered	T92,T164,T165
DataWait->Error	99	Covered	T166,T167,T168
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T22,T12
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T22,T12
Idle	-	1	0	-	Covered	T1,T22,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T22,T12
DataWait	-	-	-	0	Covered	T1,T22,T12
AckPls	-	-	-	-	Covered	T1,T22,T12
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T43

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T12
DataWait	75	Covered	T1,T2,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T15,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T146,T147
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T12
DataWait->AckPls	80	Covered	T1,T2,T12
DataWait->Disabled	107	Covered	T169
DataWait->Error	99	Covered	T37,T67,T60
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T20,T21
EndPointClear->Disabled	107	Covered	T148,T98,T149
EndPointClear->Error	99	Covered	T3,T7,T8
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T12
Idle->Disabled	107	Covered	T3,T4,T17
Idle->Error	99	Covered	T15,T16,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T12
Idle	-	1	0	-	Covered	T1,T2,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T12
DataWait	-	-	-	0	Covered	T1,T2,T12
AckPls	-	-	-	-	Covered	T1,T2,T12
Error	-	-	-	-	Covered	T3,T15,T16
default	-	-	-	-	Covered	T3,T20,T21

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T16
0	1	Covered	T4,T17,T43
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222267032	124036	0	0
FpvSecCmErrorStEscalate_A	222267032	124883	0	0
u_state_regs_A	222267032	222110796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124036	0	0
T3	16750	4838	0	0
T4	364	0	0	0
T6	0	468	0	0
T7	0	379	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	358	0	0
T16	0	522	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	415	0	0
T37	0	392	0	0
T43	1192	0	0	0
T46	0	308	0	0
T87	0	600	0	0
T108	0	411	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	124883	0	0
T3	16750	4928	0	0
T4	364	0	0	0
T6	0	469	0	0
T7	0	380	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	359	0	0
T16	0	523	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	416	0	0
T37	0	393	0	0
T43	1192	0	0	0
T46	0	309	0	0
T87	0	601	0	0
T108	0	412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0